/* IKON Corporation 2617 Western Ave Seattle, WA 98121 (206) 728-6465 */ /* 13 November 1990 */ /* 29 January 1991 changed timeout defaults to 30 seconds added minimim timeout different from default value added ioctl commands for compatibility with SUN and Versatec VME drivers. 4 February 1991 added additional ioctl commands for timeout set and register read-back that should have been included in the 29 Jan stuff. 10 September 1991 added normal print mode to documentation/comments. 18 December 1991 deleted IHCP_MINPHYS_SIZE definition. will use the system minphys() now. the maximum hardware block size is 0xffffff. anything over that will cause strategy to return with an error - and no data transfer will occur. changed timeout max and default. default now 30 minutes, was seconds. the driver is now able to accept signals (kill) while waiting for DMA done or fifo interrupts. this allows setting the timeout to a large number without locking out kill signals. added IHCPPRI - the sleep priority added signal received flag to flags in unit array. 7 January 1992 added DELAY(1) macro before each return in interrupt code to try to allow enough time for SBus interrupt line to rise slowly to the off state before the kernel re-enables interrupts. This problem occurs because of the open-collector style interrupt lines with light pull-ups. The delay is distateful, but since the interrupt routine is invoked only once per DVMA block transfer, the performance penalty is probably too small to measure. 13 April 1992 Added print/plot mode and speed defaults to this .h file. This is to make it easier for a user to change the startup defaults. It should be particularly useful when the driver is called only by cat or the lpr spooler, and there is no opportunity to make an ioctl speed or mode call in an application program. The defaults can be easily edited prior to a make. Note that the versatec compatible boards have only two speeds, so that SPEED0 = SPEED2 = slow, and SPEED1 = SPEED3 = fast for the 10104, and 10105. The 10106 supports all four speed selections. At this time, the defaults are global, and apply to all cards served by the driver. If it is necessary to provide different startup mode and speed selections for the cards served by this driver, it will be necessary to modify the ihcp.c code to explicitly set the Ihcp_lf (latched funcion) and Ihcp_ds_co (device status/command out) registers for each board. This probably should be done in the attach code. */ /************************************************************************ * * * This driver is provided at no charge to IKON's customers * * in the hope that it will assist them in understanding and * * using IKON's Sbus hardcopy interface products. This code * * is intended to be a working and (relatively!) bug free driver * * when running on the machine and OS rev available to IKON. * * IKON will attempt to keep this code running on current OS and * * hardware from SUN - and others - but does not guarantee this. * * The user is encouraged to contact IKON with comments, * * suggestions, and BUG REPORTS. * ************************************************************************/ /* definition file for users of IKON driver for Sbus hardcopy devices */ /* also used inside driver code !!! don't mess with this unless you mean it!*/ /* IKON's hardcpopy boards for the Sbus include the following: Model 10104 Versatec Differential Model 10105 Versatec TTL Model 10106 Centronics The three boards share a common register set, and all operate under the same software driver. Not all functions are supported by all boards - the software will check to make sure that a requested operation is supported for that particular board. */ /* The boards all use the LSI logic L64853 Sbus DMA controller. The D channel is used for all programmed i/o and DMA transfers to the attached printer. The E channel us unused. The register mappings are shown below. The base addresses of the two sets of registers - DMAIO and IHCP - are determined by the address bits used by the L64853 to select the register spaces. In the current implementation, bits A15 & A14 are used. This is reported by the Fcode prom, and will be transparent to the driver code. In order to reduce the loading on each Sbus address line, the IHCP registers are placed on 16 byte boundaries, and occupy 128 bytes of space. The DMAIO registers are 32 bits wide, the IHCP registers are 8 bits wide. A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAIO CSR 0 1 X X X X X X X X X X 0 0 0 X DMAIO ADD 0 1 X X X X X X X X X X 0 1 0 X DMAIO RANGE 0 1 X X X X X X X X X X 1 0 0 X IHCP LATCHED FUNCTIONS 1 0 X X X X X X X 0 0 0 X X X X IHCP INTERFACE STAT/DATA OUT 1 0 X X X X X X X 0 0 1 X X X X IHCP DEVICE STATUS/CMD/MODE OUT 1 0 X X X X X X X 0 1 0 X X X X IHCP RESET INTERRUPT FLAG 1 0 X X X X X X X 0 1 1 X X X X IHCP SOFTWARE ACK 1 0 X X X X X X X 1 0 0 X X X X IHCP MASTER CLEAR 1 0 X X X X X X X 1 0 1 X X X X IHCP FACTORY USE #0 1 0 X X X X X X X 1 1 0 X X X X IHCP FACTORY USE #1 1 0 X X X X X X X 1 1 1 X X X X */ /* ------------ DMAIO CSR Register bit assignments 31-28 R Device Id 1000 27-16 R Reserved FFF 15 RW ILAC. Write this bit to 0. 14 R TC 13 RW Enable Byte Counter = 1 12-11 R D Channel Pack Register Byte Address 10 R D Channel DMA Cycle Request 9 RW D Channel DMA Enable 1= Respond to D Chan requests 8 RW D Channel Write Operation 1 = Write memory 0 = Read memory 7 RW Reset 1 = Reset state 6 RW Drain Buffer 1 = Write D Chan Pack reg to SBus memory and clear the Pack Count (Bits 3,2). This bit clears automatically. 5 W Flush Buffer. 1 = Reset Pack Count, Err Pending and TC bits. 4 RW Interrupt Enable. 1 = Pass interrupt requests to SBus INTREQ Interrupt sources are D_IRQ*, Error Pending and TC reached. 3-2 R D Channel Pack Count. The number of valid bytes destined to be written to the SBus. 1 R Error Pending. Set if an error during a D Channel operation. Parity, protection or timeout. 0 R Interrupt Pending (1 = Asserted.). Latched OR of D_IRQ* or TC ----*/ /*--------------IHCP latched function bit definitions (latched fcns read/write) 7 IBSY RW ignore centronics BUSY - 10106 board only 6 IENB RW enable device ready & fifo empty interrupt 5 DSTR RW enable data streaming - 10106 board only 4 LRST RW latched device reset (reset true while set) 3 TIM1 RW tim1,0 select device handshake timing 2 TIM0 RW 00=slowest 1 IHNB RW enable fifo half full interrupt 0 xxxx RW latched, but not used -- reserved ----*/ /*--------------IHCP interface status bits (read only) 7 FERY R fifo empty and device ready 6 DRDY R device ready 5 INTF R interrupt flag-sets w/FERY t.e. if IENB true 4 -FFIF R 0 when fifo full 3 -FFHF R 0 when fifo half full 2 -FFEF R 0 when fifo empty 1 VSPP R 1 when versatec spp mode selected (at fifo outout) 0 VPLT R 1 when versatec plot mode selected (at fifo output) ----*/ /*--------------IHCP data out (write only) bytes written to this register are placed in the fifo and passed to the device. ----*/ /*--------------IHCP device status bits (read only) 7,6,5 DEVT R device type - indicates which board is installed 101 = 10104 = Versatec differential 011 = 10105 = Versatec TTL 110 = 10106 = Centronics 4 VRCA R Versatec ready or Centrnics ack pulse asserted 3 -BUSY R 0 = Centronics busy asserted (always 1 for Versatec) 2 CFLT R 1 = Centronics fault asserted (0 for Versatec) 1 -NPPE R 0 = paper out (always 1 for Versatec differential) 0 -VOCS R 0 = Versatec online or Centronics selected ----*/ /*--------------IHCP command/mode output bits - Versatec only (write only) versatec line terminate pulse VLTR 0 0 0 0 versatec eot pulse VEOT 0 0 0 1 Versatec form feed pulse VFED 0 0 1 0 Versatec clear pulse VCLR 0 0 1 1 set mode and clear ready ff 1 0 SP PL ( SP = simultaneous print- set mode and do not clear ready ff 1 1 SP PL plot mode PL = plot mode ) ( SP,PL = 0,0 => normal print mode ) ----*/ /*--------------IHCP reset interrupt flag (write only) any write to this register resets the IFLG bit and the associated interrupt ----*/ /*--------------IHCP software ack (write only) any write to this register is equivalent to a Centronics ack pulse, or a true-false-true sequence on the Versatec ready input. this command can be used to re-synchronize the internal device ready ff after some error conditions. ----*/ /*--------------IHCP master clear (write only) any write to this register will master clear all the IHCP logic. This command DOES NOT clear the L68453, and DOES NOT send a reset to the attached device. Master clear sets the latched function register to 0 but does not initialize the print/plot or simultaneous print plot mode at the fifo output. after master clear, or bus initialize, these modes should be explicitly set by the software. ----*/ #ifndef _IOCTL_ #include #endif /* define DMAIO register bits */ #define DMAIO_COUNT_ENABLE 0X00002000 /* 1 = enable Byte Counter, 0 = disable */ #define DMAIO_DMA_ENABLE 0X00000200 /* 1 = enable DMA operation */ #define DMAIO_DMA_RW 0X00000100 /* 1 = Write memory 0 = Read memory */ #define DMAIO_DEV_RESET 0X00000080 /* 1 = enable, 0 = disable */ #define DMAIO_DRAIN_BFR 0X00000040 /* 1 = Write back and clear, bit resets itself */ #define DMAIO_FLUSH_BFR 0X00000020 /* 1 = Reset Pack Count, Err Pending and TC bits */ #define DMAIO_INT_ENABLE 0X00000010 /* 1 = enable, 0 = disable */ #define DMAIO_TC 0X00004000 /* 1 = TC Reached */ #define DMAIO_PACK_ADR 0X00001800 /* 1 = marks the two bit address */ #define DMAIO_REQ_PEND 0X00000400 /* 1 = Active DMA request */ #define DMAIO_PACK_COUNT 0X0000000c /* 1 = marks the two bit count */ #define DMAIO_ERR_PENDING 0X00000002 /* 1 = Active, clears on read */ #define DMAIO_INT_PENDING 0X00000001 /* 1 = Active, clears on read */ /* define IKON register bits */ #define IHCP_IGNORE_BUSY 0x80 /* 1 = ignore centronics busy */ #define IHCP_RINT_ENB 0x40 /* enable fifo & dev interrupt */ #define IHCP_DATA_STREAM 0x20 /* enable centr data streaming */ #define IHCP_LONG_RESET 0x10 /* assert device reset while 1 */ #define IHCP_SPEED3 0x0C /* fastest device speed */ #define IHCP_SPEED2 0x08 #define IHCP_SPEED1 0x04 #define IHCP_SPEED0 0x00 /* slowest device speed */ #define IHCP_HINT_ENB 0x02 /* enable fifo half full int */ #define IHCP_FIFO_DEV_RDY 0x80 /* fifo empty & device ready */ #define IHCP_DEV_RDY 0x40 /* device ready */ #define IHCP_INTFLAG 0x20 /* interrupt flag */ #define IHCP_FIFO_NOT_FULL 0x10 /* 0 for fifo full */ #define IHCP_FIFO_NOT_HALF 0x08 /* 0 for fifo half full */ #define IHCP_FIFO_NOT_EMPTY 0x04 /* 0 for fifo empty */ #define IHCP_VERS_SPP 0x02 /* 1 if vers in spp mode at conn*/ #define IHCP_VERS_PLOT 0x01 /* 1 if vers in plot mode */ #define IHCP_VERS_DIFF 0xA0 /* 10104 */ #define IHCP_VERS_TTL 0x60 /* 10105 */ #define IHCP_CENTRONICS 0xC0 /* 10106 */ #define IHCP_VRDY_CACK 0x10 /* vers ready or centronics ack */ #define IHCP_C_NOT_BUSY 0x08 /* high if cent not busy */ #define IHCP_C_FAULT 0x04 /* high if cent fault asserted */ #define IHCP_PAPER_OK 0x02 /* high if paper present */ #define IHCP_OFFLINE 0x01 /* high if offline or !selected */ #define IHCP_VLTR 0x00 /* remote line term command */ #define IHCP_VEOT 0x01 /* remote eot command */ #define IHCP_VFED 0x02 /* remote form feed command */ #define IHCP_VCLR 0x03 /* remote clear command */ #define IHCP_MODESET_RYOFF 0x08 /* set mode and clear rdy ff */ #define IHCP_MODESET_RYON 0x0c /* set mode and leave ryff set */ #define IHCP_SPP_MODE 0x02 /* sets spp mode w/above */ #define IHCP_PLOT_MODE 0x01 /* sets plot mode w/above */ #define IHCP_NORM_PRINT 0x00 /* normal print mode, no spp */ /* use IHCP_MODESET_xxx with spp mode and / or plot mode to set mode */ /* the ioctl() function call looks like: ioctl(filedescriptor,command,argument) argument is used in some of the ihcp ioctl calls to provide values to the driver ioctl routine, or return values to the calling program. In one case - data out - it contains an array of charater data to be sent to the attached device. the argument is restricted to a maximum of 255 bytes - by unix, and by the driver. the following ioctl commands are available to programs using the ihcp driver: IHCPIO_DEV_RESET reset attached device IHCPIO_SET_CONFIG select device timing and busy mode w/ value in arg IHCPIO_SET_DMATIME set dma timeout to arg seconds IHCPIO_SET_RDYTIME set fifo <1/2 full and fifo empty+device ready timeout to arg seconds IHCPIO_GET_REGS return board's registers in arg IHCPIO_GET_STATUS return device status in arg IHCPIO_GET_BOARD return board type in arg IHCPIO_SET_VMODE set versatec print/plot/spp mode using value in arg IHCPIO_SET_VMODEX same as VMODE, but clear ready sync ff - most plotters will use VMODE - both for versatec only IHCPIO_V_CMD send pulse command to plotter using value in arg (versatec only) IHCPIO_DATA_OUT send data bytes from arg array to device. byte count in IHCPIO_COUNT_MASK portion of cmd IHCPIO_RDY_WAIT wait for fifo empty and device ready IHCPIO_HALF_WAIT wait for fifo less than 1/2 full IHCPIO_STREAM_ON select data streaming mode (centronics only) IHCPIO_STREAM_OFF clear data streaming mode IHCPIO_GET_FLAGS returns unit_flags in arg IHCPIO_GET_FIFO returns fifo status in arg */ /* the ioctl command codes conform to the unix pattern: the top 3 bits of the 32 bit value indicate whether arguments are to be copied in, copied out, both, or neither. 0x80000000 = copy in 0x40000000 = copy out 0x20000000 = no argument transfer 0xC0000000 = copy in and out the number of bytes in the argument is encoded in the lower 8 bits of the upper half of the u_int, and the actual command is encoded in the lower half. a rather arbitrary character, which is intended to identify the driver, is also encoded in the lower half of the command. it becomes part of the command value. for all commands except DATA_OUT, the arg length is part of the command value. WHEN USINT THE IHCP_DATA_OUT IOCTL, THE CALLING PROGRAM IS REQUIRED TO COMBINE THE ARGUMENT LENGTH WITH THE IOCTL COMMAND AS FOLLOWS: cmd = IHCP_DATA_OUT | ( ( arg_length & 0xFF ) << 16 ) ; commands which require arguments - in or out - will pass those values as 32 bit unsigned integers. the only exception is the DATA_OUT ioctl, which uses an array of up to 255 bytes as its argument. the magic character that identifies this driver is hereby (arbitrarily) chosen to be 'H'. the following ioctl commands are defined using pre-existing ioctl command macros. the CMD_MASK and COUNT_MASK values defined MUST match the usage in ioccom.h. refer to that include file for further information. ADDITIONAL IOCTL COMMANDS AND ARGUMENTS ARE FOUND AT THE END OF THIS FILE. THEY ARE INCLUDED FOR COMPATIBILITY WITH SUN AND VERSATEC DRIVERS FOR THE 10088 VME BOARD, AND WILL HOPEFULLY BE COMPATIBLE WITH OTHER MANUFACTURERS BOARDS AND DRIVERS (SHOULD THERE BE ANY!) the "magic character" for these commands is "v" */ #define IHCPIO_CMD_MASK 0xE000FFFF /* cmd in top 3 and bottom 16 bits */ #define IHCPIO_COUNT_MASK 0x00FF0000 /* arg byte count here */ /* dev_reset and stream on & off don't affect other latched function bits*/ #define IHCPIO_DEV_RESET _IO(H,0) /* reset attached device */ /* sets & resets latched reset */ #define IHCPIO_SET_CONFIG _IOW(H,1,int) /* ignore busy, speed selection */ /* config bit patterns: larg[0] = IGNORE_BUSY | SPEEDx */ #define IHCPIO_SPEED0 0x00000000 /* slowest device speed */ #define IHCPIO_SPEED1 0x00000004 #define IHCPIO_SPEED2 0x00000008 #define IHCPIO_SPEED3 0x0000000C /*fastest device timing */ #define IHCPIO_IGNORE_BUSY 0x00000080 /* ignore centr busy */ #define IHCPIO_SET_DMATIME _IOW(H,2,int) /* set dma timeout to arg secs */ #define IHCPIO_SET_FIFOTIME _IOW(H,3,int) /* set wait for <1/2 full or */ /* empty and dev rdy timeout */ #define IHCPIO_GET_REGS _IORN(H,4,24) /* puts all regs in arg array */ /* returns all board registers. DMAIO registers are all 32 bits wide. IHCP registers are 8 bits wide. each is returned in a 32 bit longword in the following order: (u_long larg[6]) larg[0] = DMAIO CSR larg[1] = DMAIO ADD larg[2] = DMAIO RANGE larg[3] = IHCP LATCHED FUNCTIONS larg[4] = IHCP INTERFACE STATUS larg[5] = IHCP DEVICE STATUS */ #define IHCPIO_GET_STATUS _IOR(H,5,int) /* returns FORMATTED device */ /* status - not like dump regs */ #define IHCPIO_DEV_RDY 0x00000010 /* v-rdy or centr ack asserted*/ #define IHCPIO_DEV_BUSY 0x00000008 /* centronics asserting busy */ #define IHCPIO_DEV_FAULT 0x00000004 /* centronics asserting fault */ #define IHCPIO_DEV_POUT 0x00000002 /* v or c no paper */ #define IHCPIO_DEV_SEL 0x00000001 /* v online or c selected */ #define IHCPIO_GET_BOARD _IOR(H,6,int) /* gets board type */ #define IHCPIO_VERS_DIFF 0x000000A0 /* model 10104 */ #define IHCPIO_VERS_TTL 0x00000060 /* model 10105 */ #define IHCPIO_CENT 0x000000C0 /* model 10106 */ #define IHCPIO_SET_VMODE _IOW(H,7,int) /* sets print/plot, spp - LEAVES*/ /* READY FF ON */ #define IHCPIO_SET_VMODEX _IOW(H,8,int) /* same as above, but CLEARS RDY*/ /* FF & WAITS FOR READY */ #define IHCPIO_V_SPP 0x00000002 /* sets spp w/MODE(X) */ #define IHCPIO_V_PLOT 0x00000001 /* sets plot mode w/MODE(X)*/ #define IHCPIO_V_NPRINT 0x00000000 /* 0 = normal print mode */ #define IHCPIO_V_CMD _IOW(H,9,int) /* pulse commands to versatec */ #define IHCPIO_VLTR 0x00000000 /* remote line terminate*/ #define IHCPIO_VEOT 0x00000001 /* remote eot */ #define IHCPIO_VFED 0x00000002 /* remote form feed */ #define IHCPIO_VCLR 0x00000003 /* remote buffer clear */ #define IHCPIO_DATA_OUT _IOWN(H,10,0) /* CALLING PGM WILL AND IN THE */ /* ACTUAL CHARACTER COUNT - DONE*/ /* THIS WAY SO COUNT CAN BE A */ /* VARAIBLE, NOT CONSTANT !!! */ /* sends char array in ARG to */ /* fifo if room. if not - return*/ /* EINVAL. will flag error if */ /* caller tries to send more */ /* 255 bytes, or if fifo becomes*/ /* full during transfers. */ #define IHCPIO_RDY_WAIT _IO(H,11) /* waits for fifo empty and */ /* device ready */ #define IHCPIO_HALF_WAIT _IO(H,12) /* wait for fifo