/* IKON Corporation 2617 Western Ave. Seattle, WA 98121 (206) 728-6465 unit structure definition file for Solaris 2.x driver for PCI DR11-W emulators 1 October, 1996 initial version for SPARC 17 June, 1997 added register state save structure for power management - suspend and resume added default configuration variables to soft state 27 August, 1997 moved dma_handle to soft state added endian reg to saved state 15 September, 1997 added dma chaining for x86 added dma_attr structures to soft state for data & iopbs 7 June, 2000 made idr and plx bases volatile 16 June, 2000 chucked the whole high-level interrupt thing in favor of a single mutex. this to try to solve weird problems on some machines that caused wakeups to be missed, or not issued at all added int_line to unit struct */ /************************************************************************ * * * This driver is provided at no charge to IKON's customers * * in the hope that it will assist them in understanding and * * using IKON's PCI DR11-W emulators (10116 & 10118). This code * * is intended to be a working and (relatively!) bug free driver * * when running on the machine and OS rev available to IKON. * * IKON will attempt to keep this code running on current OS and * * hardware from SUN - and others - but does not guarantee this. * * The user is encouraged to contact IKON with comments, * * suggestions, and BUG REPORTS. * ************************************************************************/ #ifndef _IDR_VAR_H #define _IDR_VAR_H #endif struct idr_unit { dev_info_t *dip; /* devinfo pointer */ kmutex_t mutex; /* mutex lock for interrupt */ kcondvar_t cv; /* conditional variable for waits */ kcondvar_t power_cv; /* cv for power management waits */ ddi_iblock_cookie_t iblock_cookie; /* interrupt iblock cookie */ volatile u_long plx_base; /* points at mapped plx registers */ volatile u_long idr_base; /* points at mapped idr registers */ u_long iopb_base; /* points at mapped iopb area */ ddi_acc_handle_t config_acc_handle; /* config reg access handle */ ddi_acc_handle_t plx_acc_handle; /* plx reg access handle */ ddi_acc_handle_t idr_acc_handle; /* idr reg access handle */ ddi_acc_handle_t iopb_acc_handle; /* iopb access handle */ u_long iopb_phys_base_addr; /* physical iopb base address */ ddi_dma_handle_t dma_handle; /* dma handle */ ddi_dma_handle_t iopb_handle; /* iopb handle */ ddi_dma_attr_t dma_attr; /* dma attr struct for user dma buffer */ ddi_dma_attr_t iopb_attr; /* dma attr struct for iopb chain */ struct buf *buf_p; /* will point at buffer in use */ volatile u_int unit_open; /* 1 = open */ volatile u_int unit_attached; /* 1 = attached */ volatile u_long unit_flags; /* our flag bits here */ u_int dma_time; /* dma timeout # in secs */ u_int attn_time; /* attention wait timeout # */ u_int rdy_time; /* ready wait timeout # */ u_long read_fcn; /* use at read start */ u_long write_fcn; /* use at write start */ u_long read_pulse; /* pulse at read start */ u_long write_pulse; /* pulse at write start */ u_int saved_instance; /* for error logging, etc */ u_long dev_and_vendor_id; /* device and vendor id from config regs*/ u_long revision_id; /* revision id from config regs */ u_int range_resid; /* remaining count to xfer */ /* may be used for multi-dma */ /* per dr11 blocks (unused?) */ u_long saved_plx_endian_reg; /* (suspend) saved plx endian reg */ u_long saved_plx_int_cstat; /* saved plx int control/status */ u_long saved_plx_eeprom_user; /* saved plx eeprom control & user bits */ u_long saved_latched_functions;/* saved 116 latched fcn register */ u_long saved_mode; /* saved 116 mode */ u_long saved_range_low; /* saved low range (unnecessary -probably)*/ u_long saved_range_mid; /* saved mid range */ u_long saved_range_high; /* saved high range */ volatile u_int unit_suspended; /* suspended for system power down */ u_int dma_time_def; /* default dma wait - IN SECONDS */ u_int attn_time_def; /* default attn wait - IN SECONDS */ u_int rdy_time_def; /* default rdy wait - IN SECONDS */ u_long read_fcn_def; /* read fcn default */ u_long write_fcn_def; /* write fcn default */ u_long read_pulse_def; /* read pulse default */ u_long write_pulse_def; /* write pulse default */ u_long endian_def; /* endian default */ u_long latch_reg_def; /* latched functions default */ u_long mode_reg_def; /* mode register default */ u_int sg_list_length; /* # of 16 byte entries in scatter/gather list */ u_char int_line; /* assigned pci interrupt line */ } ; /* plx_base and idr_base are returned by ddi_regs_map_setup, which expects them to be caddr_t types if i declare them that way, then when i add an offset and cast to (u_long *) for the calls to ddi_getl and ddi_putl, lint gets upset about possible alignment problems, even though the result is correct, since the offsets are (so far) multiples of 4 as long as u_long and caddr_t remain the same size and the 64 bit compiler doesn't change the size of caddr, this should be ok i want to keep the offsets as byte addresses, for readability, and because someday i may need to use them in ..getb or something */