/* * idr_var.h * * unit structure definition file for Solaris 7 & later driver for * Tahoma Technology 10116/10118 PCI DR11-W emulators * * Tahoma Technology * (formerly Ikon Corporation) * 107 2nd Avenue North * Seattle, WA, USA 98109 * * 206.728.6465 * http://www.tahomatech.com * tahoma@tahomatech.com * * This driver (including source) is placed in the public domain in the * hope that it will prove useful in using and understanding Tahoma Technolgy's * 10116 and 10118 PCI DR11-W emulators. * * This code is intended to be working and (relatively) bug free driver when * running on the host computers and operating systems available to Tahoma Technology. * Tahoma Technology will attempt to keep the code running on contemporary OSs * and hardware from SUN and others, but does not guarantee this. * * References to Ikon Corporation left in place for compatibility and historical reasons. * * 1 October, 1996 initial version for SPARC * * 17 June, 1997 added register state save structure for power management - * suspend and resume * * added default configuration variables to soft state * * 27 August, 1997 moved dma_handle to soft state * * added endian reg to saved state * * 9 July, 1998 modified for compatibility with 64 bit Solaris * * added ignore minphys parameter * * 4 May, 2004 changed IKON to Tahoma */ /************************************************************************ * * * This driver is provided at no charge to IKON's customers * * in the hope that it will assist them in understanding and * * using IKON's PCI DR11-W emulators (10116 & 10118). This code * * is intended to be a working and (relatively!) bug free driver * * when running on the machine and OS rev available to IKON. * * IKON will attempt to keep this code running on current OS and * * hardware from SUN - and others - but does not guarantee this. * * The user is encouraged to contact IKON with comments, * * suggestions, and BUG REPORTS. * ************************************************************************/ #ifndef _IDR_VAR_H #define _IDR_VAR_H #endif struct idr_unit { dev_info_t *dip; /* devinfo pointer */ kmutex_t soft_mutex; /* mutex lock for soft interrupt */ kmutex_t high_mutex; /* mutex lock for hig level interrupt */ kcondvar_t cv; /* conditional variable for waits */ kcondvar_t power_cv; /* cv for power management waits */ ddi_iblock_cookie_t soft_iblock_cookie; /* soft interrupt iblock cookie */ ddi_iblock_cookie_t high_iblock_cookie; /* high interrupt iblock cookie */ ddi_softintr_t soft_intr_id; /* identifies soft interrupt routine */ caddr_t plx_base; /* points at mapped plx registers */ caddr_t idr_base; /* points at mapped idr registers */ ddi_acc_handle_t config_acc_handle; /* config reg access handle */ ddi_acc_handle_t plx_acc_handle; /* plx reg access handle */ ddi_acc_handle_t idr_acc_handle; /* idr reg access handle */ ddi_dma_handle_t dma_handle; /* dma handle */ struct buf *buf_p; /* will point at buffer in use */ volatile u_int unit_open; /* 1 = open */ volatile u_int unit_attached; /* 1 = attached */ volatile u_int soft_intr_req; /* 1 = high level has req-d soft intr */ volatile uint32_t unit_flags; /* our flag bits here */ clock_t dma_time; /* dma timeout # in secs */ clock_t attn_time; /* attention wait timeout # */ clock_t rdy_time; /* ready wait timeout # */ uint32_t read_fcn; /* use at read start */ uint32_t write_fcn; /* use at write start */ uint32_t read_pulse; /* pulse at read start */ uint32_t write_pulse; /* pulse at write start */ u_int saved_instance; /* for error logging, etc */ uint32_t dev_and_vendor_id; /* device and vendor id from config regs*/ uint32_t revision_id; /* revision id from config regs */ u_int range_resid; /* remaining count to xfer */ /* may be used for multi-dma */ /* per dr11 blocks (unused?) */ uint32_t saved_plx_endian_reg; /* (suspend) saved plx endian reg */ uint32_t saved_plx_int_cstat; /* saved plx int control/status */ uint32_t saved_plx_eeprom_user; /* saved plx eeprom control & user bits */ uint32_t saved_latched_functions;/* saved 116 latched fcn register */ uint32_t saved_mode; /* saved 116 mode */ uint32_t saved_range_low; /* saved low range (unnecessary -probably)*/ uint32_t saved_range_mid; /* saved mid range */ uint32_t saved_range_high; /* saved high range */ volatile u_int unit_suspended; /* suspended for system power down */ clock_t dma_time_def; /* default dma wait - IN SECONDS */ clock_t attn_time_def; /* default attn wait - IN SECONDS */ clock_t rdy_time_def; /* default rdy wait - IN SECONDS */ uint32_t read_fcn_def; /* read fcn default */ uint32_t write_fcn_def; /* write fcn default */ uint32_t read_pulse_def; /* read pulse default */ uint32_t write_pulse_def; /* write pulse default */ uint32_t endian_def; /* endian default */ uint32_t latch_reg_def; /* latched functions default */ uint32_t mode_reg_def; /* mode register default */ u_int ignore_minphys; /* if one, ignore system minphys */ } ; /* plx_base and idr_base are returned by ddi_regs_map_setup, which expects them to be caddr_t types the get and put functions require pointers to fixed types i will probably have to cast the caddr_t to uint64_t, add teh offset, and tehn cast to uint32_t * to keep lint happy i want to keep the offsets as byte addresses, for readability, and because someday i may need to use them in ..getb or something */