/* * idr_io.h * * ioctl and default definition file for Solaris 7 & later driver for * Tahoma Technology 10116/10118 PCI DR11-W emulators * * Tahoma Technology * (formerly Ikon Corporation) * 107 2nd Avenue North * Seattle, WA, USA 98109 * * 206.728.6465 * http://www.tahomatech.com * tahoma@tahomatech.com * * This driver (including source) is placed in the public domain in the * hope that it will prove useful in using and understanding Tahoma Technolgy's * 10116 and 10118 PCI DR11-W emulators. * * This code is intended to be working and (relatively) bug free driver when * running on the host computers and operating systems available to Tahoma Technology. * Tahoma Technology will attempt to keep the code running on contemporary OSs * and hardware from SUN and others, but does not guarantee this. * * References to Ikon Corporation left in place for compatibility and historical reasons. * * * 1 October, 1996 initial version for SPARC * * 17 June, 1997 added PLX DMA PCI ADD to GET_REGS ioctl * * 9 July, 1998 modified for compatibility with 64 bit Solaris * * added ignore_minphys default parameter * * 4 May, 2004 changed IKON to Tahoma */ /* this file is to be #include(d) in the program that calls the 10116/10118 driver. it is also used internally by the driver - don't modify this unless you know what you are doing!!!! the PCI driver attempts to maintain ioctl command and argument compatibility with the Sbus driver. some Sbus ioctls used the Sbus register include file for the bit definitions of arguments. this driver will move those old compatibility definitions into this _io.h file as sub-defines to command defines. including this file in the calling program will also cause idr_reg.h to be included. this makes register bit defines available - to be used in the ioctls that access and report the state of the pci board's registers. see idr_reg.h for bit definitions. some new ioctls are added to allow direct access to new registers, and to PCI configuration data that wasn't available in the Sbus version */ #ifndef _SYS_IOCCOM_H #include #endif /* pick up register definitions for use by calling program - if not already included */ #ifndef _IDR_REG_H #include "./idr_reg.h" #endif /* the ioctl() function call looks like: ioctl(filedescriptor,command,argument) commands which require arguments - in or out - will pass those values as 32 bit unsigned integers (whether in 32 or 64 bit system) argument is used in some of the idr ioctl calls to provide values to the driver ioctl routine, or return values to the calling program. the argument is restricted to a maximum of 255 bytes - by unix, and by the driver. the following ioctl commands are available to programs using the idr driver: IDRIO_SET_MODE sets the mode register bits and the RDIS bit in the latched functions register - Sbus compatibility IDRIO_IMM_FCN sets the function bits immediately IRDIO_READ_FCN sets the function bits before each block read IDRIO_WRITE_FCN sets the function bits before each block write IDRIO_IMM_PULSE issues pulse commands immediately IDRIO_READ_PULSE issues pulse commands at each block read IDRIO_WRITE_PULSE issues pulse commands at each block write IDRIO_SET_DMA_TIME sets dma timeout value IDRIO_SET_ATTN_TIME sets wait for attention timeout value IDRIO_SET_RDY_TIME sets wait for ready timeout value IDRIO_ATTN_WAIT waits for attention 0-to-1 transition IDRIO_RDY_WAIT waits for READY IDRIO_GET_STATUS gets flags/status register - Sbus compatibility IDRIO_GET_RANGE gets range counter value IDRIO_GET_REGS gets all registers including PLX chip's note that latch reg bit DMIN is forced to 1 by this ioctl(to allow reading data in reg) IDRIO_GET_FLAGS returns various driver flag and error bits - Sbus compatibility IDRIO_DATA_OUT writes 16 bits to DR11 output latches (in bottom of 32 bit arg) IDRIO_DATA_IN reads 16 bits from DR11 input latches (into bottom of 32 bit arg) IDRIO_SET_RANGE sets DR11 range counter in manual mode IDRIO_AUTO selects auto mode (default). auto mode causes DR11 range & controls to be set up for each read/write call at same time as DMA logic is set up. DMA and DR11 blocks are set to the same size, and a single DMA block is used per DR11 block. in auto mode, all that is necessary to do dma transfers is read or write calls. IDRIO_MANUAL selects manual mode. manual mode causes read/write calls to set up DMA controller only. DR11 range and controls must be set up explicitly by calling pgm. manual mode allows multiple read/write calls per DR11 block, or disabling the DR11 range counter and doing continuous transfers. IDRIO_START_READ IDRIO_START_WRITE in manual mode, enables overall block-issued before DR11 logic is enabled with GO command. and before the first unix read or write call. IDRIO_BLOCK_END in manual mode, disables overall block transfer-issued after all DR11 transfers are complete, typically after a wait for ready has returned successfully. *** new ioctl commands for PCI DR11-W emulators *** IDRIO_DEV_AND_VEND_ID return board device and vendor ids in arg IDRIO_REVISION_ID return board revision level in arg IDRIO_SET_NEW_MODE set PCI DR11 mode IDRIO_GET_NEW_STATUS get PCI device status IDRIO_GET_NEW_FLAGS get PCI flag bits IDRIO_MASTER_CLEAR reset board - use only in dire emergencies! */ /* the ioctl command codes conform to the unix pattern: the top 3 bits of the 32 bit value indicate whether arguments are to be copied in, copied out, both, or neither. 0x80000000 = copy in 0x40000000 = copy out 0x20000000 = no argument transfer 0xC0000000 = copy in and out the number of bytes in the argument is encoded in the lower 8 bits of the upper half of the u_int, and the actual command is encoded in the lower half. a rather arbitrary character, which is intended to identify the driver, is also encoded in the lower half of the command. it becomes part of the command value. for all commands the arg length is part of the command value. commands which require arguments - in or out - will pass those arguments as 32 bit unsigned integers, including the DATA_IN and DATA_OUT ioctls, which use the bottom 16 bits of the 32 bit argument the magic character that identifies this driver is hereby (arbitrarily) chosen to be 'D'. the following ioctl commands are defined using pre-existing ioctl command macros. the CMD_MASK and COUNT_MASK values defined MUST match the usage in ioccom.h. refer to that include file for further information. */ #define IDRIO_CMD_MASK 0xE000FFFF /* cmd in top 3 and bottom 16 bits */ #define IDRIO_COUNT_MASK 0x00FF0000 /* arg byte count here */ /* THE SOLARIS 2.x MACROS IN ioccom.h WANT THE "MAGIC LETTER' QUOTED. THE SOLARIS 1.x MACROS WANTED IT WITHOUT QUOTES SOME VERSIONS OF ioccom.h DIDN`T INCLUDE _IORN AND _IOWN. SOL2 SEEMS TO HAVE THEM */ #define IDRIO_SET_MODE _IOW('D',1,uint32_t) /* set mode reg bits & RDIS in latched reg */ /* Sbus compatibility ioctl - define old bits */ #define IDR_RDYT 0x80 /* long ready timing */ #define IDR_FMOD 0x40 /* not used in pci version */ #define IDR_BDIS 0x20 /* disable cycle req b */ #define IDR_SWAP 0x10 /* byte swap - not currently supported in pci */ #define IDR_CRQP 0x08 /* selects crq falling edge active */ #define IDR_BSYP 0x04 /* selects busy active high */ #define IDR_SPEED_MASK 0x03 /* two bits select handshake speed */ #define IDR_SPD_0 0x00 /* fastest timing */ #define IDR_SPD_1 0x01 #define IDR_SPD_2 0x02 #define IDR_SPD_3 0x03 #define IDR_RDISX 0x2000 /* disable range counter */ #define IDRIO_IMM_FCN _IOW('D',2,uint32_t) /* set function bits NOW - immediate write to fcn bits */ /* define old bits for Sbus driver compatibility */ #define IDR_FCN3 0x08 /* function bits */ #define IDR_FCN2 0x04 #define IDR_FCN1 0x02 #define IDR_FMASK 0x0E /* all function bits */ #define IDRIO_READ_FCN _IOW('D',3,uint32_t) /* set fcn bits at read start - fcn write deferred until*/ /* following (and all later) read calls */ #define IDRIO_WRITE_FCN _IOW('D',4,uint32_t) /* set fcn bits at write time - as in read_fcn above */ #define IDRIO_IMM_PULSE _IOW('D',5,uint32_t) /* issue pulses NOW - immediate write to pulse reg */ /* masked to allow only device pulses */ /* define old bits for Sbus driver compatibility */ #define IDR_RATN 0x40 /* clear attention flag */ #define IDR_TERM 0x20 /* set ready true */ #define IDR_MCLR 0x10 /* master clear idr logic - NOT FOR FRIVOLOUS USE */ #define IDR_INIT 0x08 /* send init pulse to device */ #define IDR_ACF2 0x04 /* send acf2 pulse to device */ #define IDR_CYCL 0x02 /* force cycle */ #define IDR_GO 0x01 /* send go and enable dr11 transfers */ #define OLD_PULSE_MASK IDR_RATN | IDR_TERM | IDR_INIT | IDR_ACF2 | IDR_CYCL | IDR_GO #define IDRIO_READ_PULSE _IOW('D',6,uint32_t) /* issue pulses at read start - pulses deferred until */ /* next(and later) read calls */ #define IDRIO_WRITE_PULSE _IOW('D',7,uint32_t) /* issue pulses at write time - as in read_pulse above */ #define IDRIO_SET_DMA_TIME _IOW('D',8,uint32_t) /* DVMA block timeout in secs - also controls EOR */ /* timeout in auto mode. manual eor timeout uses */ /* RDY_TIME */ #define IDRIO_SET_ATTN_TIME _IOW('D',9,uint32_t) /* ATTENTION wait timeout # */ #define IDRIO_SET_RDY_TIME _IOW('D',10,uint32_t) /* READY wait timeout in secsonds */ #define IDRIO_ATTN_WAIT _IO('D',11) /* wait for ATTENTION flag */ #define IDRIO_RDY_WAIT _IO('D',12) /* wait for DR11 READY */ #define IDRIO_GET_STATUS _IOR('D',13,uint32_t) /* returns Sbus style DR11 status & flags reg */ /* Sbus compatibility ioctl - define old bits */ #define IDR_EORF 0x80 /* DR11 end-of-range flag */ #define IDR_ATTF 0x40 /* attention flag */ #define IDR_ATTN 0x20 /* actual attention signal */ #define IDR_MCER 0x10 /* multi-cycle error flag */ #define IDR_STAT_MASK 0x0E /* mask for device status bits */ #define IDR_STTA 0x08 /* status bits from device */ #define IDR_STTB 0x04 #define IDR_STTC 0x02 #define IDR_REDY 0x01 /* master DR11 ready bit (0=block xfer enabled) */ #define IDRIO_GET_RANGE _IOR('D',14,uint32_t) /* returns DR11 range register - gets actual register */ /* bits which are initially set to the WORD count */ /* minus 1 and decrement per DR11 16 bit transfer */ #define IDRIO_GET_REGS _IORN('D',15,76) /* puts registers in arg */ /* returns all "IDR" registers and some "PLX" registers. also returns device IDs and revision level. PLX registers are all 32 bits wide. DR11 registers are 8 bits wide. except the data in register which is 16 bits wide. each is returned in a 32 bit longword in as shown below. the DMA registers returned are either channel 0 or 1, depending on which is used in the particular revision of the board. (uint32_t uarg[19]) uarg[0] = device ID (high 16 bits) & vendor ID (low 16 bits) uarg[1] = revision ID uarg[2] = PLX interrupt control/status uarg[3] = PLX EEPROM control and user bits uarg[4] = PLX DMA mode uarg[5] = PLX DMA PCI address uarg[6] = PLX DMA local address uarg[7] = PLX DMA transfer count uarg[8] = PLX DMA descriptor pointer uarg[9] = PLX DMA command/status register uarg[10] = latched functions uarg[11] = flags uarg[12] = status uarg[13] = mode uarg[14] = DR11 range counter low byte uarg[15] = DR11 range counter mid byte uarg[16] = DR11 range counter high byte uarg[17] = fifo status uarg[18] = data in */ #define IDRIO_GET_FLAGS _IOR('D',16,uint32_t) /* returns driver unit_flags */ #define IDR_DVMA_WAIT 0x80000000 /* waiting for t/c */ #define IDR_EOR_WAIT 0x40000000 /* waiting for EOR */ #define IDR_ATTN_WAIT 0x20000000 /* waiting for attention */ #define IDR_RDY_WAIT 0x10000000 /* waiting for ready */ #define IDR_DVMA_TIMEOUT 0x08000000 /* dma wait timed out */ #define IDR_EOR_TIMEOUT 0x04000000 /* eor wait timeout */ #define IDR_ATTN_TIMEOUT 0x02000000 /* attn timeout */ #define IDR_RDY_TIMEOUT 0x01000000 /* ready wait timeout */ #define IDR_MANUAL 0x00800000 /* manual mode */ #define IDR_INPUT 0x00400000 /* used w/waiting-for */ /* indicates xfer dir */ #define IDR_MCYL_ERR 0x00200000 /* multicycle error */ #define IDR_SIG_RECEIVED 0x00100000 /* sleep term'd by signal */ #define IDR_PAR_ERR 0x00080000 /* DR11 parity error - new for pci */ /* idr_clear_flags used to reset the above flags (INSIDE DRIVER ONLY!!!!!!) */ #define IDR_CLEAR_FLAGS ~(IDR_DVMA_WAIT|IDR_EOR_WAIT|IDR_ATTN_WAIT|\ IDR_RDY_WAIT|IDR_DVMA_TIMEOUT|IDR_EOR_TIMEOUT|IDR_ATTN_TIMEOUT|IDR_RDY_TIMEOUT\ |IDR_MCYL_ERR|IDR_SIG_RECEIVED|IDR_PAR_ERR) #define IDRIO_DATA_OUT _IOW('D',17,uint32_t) /* 16 bits to DR11 output reg */ #define IDRIO_DATA_IN _IOR('D',18,uint32_t) /* reads DR11 input reg */ #define IDRIO_SET_RANGE _IOW('D',19,uint32_t) /* sets DR11 range register to arg - arg should be */ /* desired WORD count minus 1 */ #define IDRIO_AUTO _IO('D',20) /* selects manual mode - auto is defaule */ #define IDRIO_MANUAL _IO('D',21) /* selects manual mode - manual requires direct control */ /* of DR11 range count and block start and end by user */ #define IDRIO_START_READ _IO('D',22) /* enables overall block xfer - manual mode only! */ #define IDRIO_START_WRITE _IO('D',23) /* enables write block transfer */ #define IDRIO_BLOCK_END _IO('D',24) /* terminates block xfers - required in manual mode - */ /* not used in auto mode */ /* start read or write enables the DR11 control logic. block end disables it start read or write should be issued before the first unix read or write call in manual mode. these ioctls do not issue a go or cycle pulse, that must be done by the calling program AFTER the start ioctl. */ /* *** new ioctls for PCI DR11 *** */ #define IDRIO_DEV_AND_VEND_ID _IOR('D',25,uint32_t) /* returns device and vendor ids in arg */ /* vendor id is low 16 bits, device id is high 16 bits */ #define IDRIO_REVISION_ID _IOR('D',26,uint32_t) /* returns board revision level in arg */ #define IDRIO_SET_NEW_MODE _IOW('D',27,uint32_t) /* sets PCI DR11 mode */ #define IDRIO_GET_NEW_STATUS _IOR('D',28,uint32_t) /* gets PCI DR11 status register */ #define IDRIO_GET_NEW_FLAGS _IOR('D',29,uint32_t) /* gets PCI DR11 flags register */ #define IDRIO_MASTER_CLEAR _IO('D',30) /* full reset of board - emergencies only! */ /* define various flags and constants these are the defaults used by the ddi_getprop() calls in idr_attach they should not be modified changes to the driver default behavior are made by editing idr.conf, and re-loading the driver */ #define DMA_TIME_MAX 600 /* protect against hanging if caller asks for giant # */ #define ATTN_TIME_MAX 600 #define RDY_TIME_MAX 600 #define DMA_TIME_MIN 10 /* try to prevent timeout during legit dma or wait */ #define ATTN_TIME_MIN 10 #define RDY_TIME_MIN 10 #define IGNORE_MINPHYS_DEF 0 /* use system minphys if 0 */ #define SPEED_DEF 0 /* handshake speed default */ #define DMA_TIME_DEF 30 /* dma time-out default seconds */ #define ATTN_TIME_DEF 30 /* fifo empty and <1/2 full time-out */ #define RDY_TIME_DEF 30 /* ready wait time default */ #define BYTE_SWAP_DEF 0 /* don't swap bytes (for SPARC, this means swap bytes) */ #define CYCLE_POL_DEF 0 /* cycle req rising edge active */ #define BUSY_POL_DEF 0 /* busy asserted low */ #define WRITE_CYCLE_DEF 1 /* issue soft cycle on write */ #define READ_CYCLE_DEF 0 /* not on read */ #define READ_ACF2_DEF 0 /* do not pulse aclo fcn2 on read (&never on write) */ #define OPEN_F3_DEF 0 /* function bit defaults for idr_open() time */ #define OPEN_F2_DEF 0 #define OPEN_F1_DEF 0 #define WRITE_F3_DEF 1 /* function bit defaults for write block */ #define WRITE_F2_DEF 0 #define WRITE_F1_DEF 0 #define READ_F3_DEF 1 /* function bit defaults for read block */ #define READ_F2_DEF 0 #define READ_F1_DEF 1