# idr.conf
#
# Configuration file for Tahoma Technology 10116/10118 PCI DR11-W driver (Solaris 7)
#
#	idr.conf
#
#	Tahoma Technology
#	(formerly Ikon Corporation)
#	107 2nd Avenue North
#	Seattle, WA, USA 98109
#
#	206.728.6465
#	http://www.tahomatech.com
#	tahoma@tahomatech.com 
#
#	9 July, 1998	added ignore_minphys parameter
#	4 May, 2004	Change IKON to Tahoma
#
#
#	Hardware configuration file for Tahoma Technology PCI DR11
#	interface driver.
#
#	This file contains driver configuration defaults, and forces the interrupt priority
#	to a value that keeps the scheduler happy.
#
#	Several driver default paramaters can be set by modifying this file and re-loading the driver.
#	This avoids having to re-compile the driver when it is necessary to change defaults.
#
#	ALL DEFAULTS APPLY TO ALL BOARD INSTANCES (this may change later)
#
#
#	START OF USER-CONFIGURABLE DEFAULTS
#
#	The handshake speed of the DR11 interface is set by the speed_def property.
#	Permissible values are 0,1,2, or 3.  0 gives the fastest speed.
#	See the board manual for details.
#
speed_def=0;
#
#	There are three software timeout clocks used by the driver: a dma timer, a wait-for-ready timer,
#	and a wait for ATTENTION timer.
#	The defaults for these timers are set by dma_time_def, rdy_time_def, and attn_time_def in SECONDS.
#
dma_time_def=30;
rdy_time_def=30;
attn_time_def=30;
#
#	The big vs little endian mode of the board is determined by the byte_swap property.
#	0 causes the data sent/received via the DR11 cable to match the byte ordering of the
#	CPU, 1 causes the data within each 16-bit word to be byte-swapped.
#
byte_swap_def=0;
#
#	The default polarities of the DR11 signals CYCLE REQUEST and BUSY are determined by the
#	cycle_pol_def and busy_pol_def properties, respectively.  Cycle_plo_def = 0 causes the
#	CYCLE REQUEST input to assert on a rising edge; 1 selects falling edge active.  Busy_pol_def
#	= 0 causes BUSY to be asserted low, 1 selects high assertion.
#
cycle_pol_def=0;
busy_pol_def=0;
#
#	At the beginning of a DR11 block, it may be necessary to issue a software cycle pulse to
#	begin the block transfer (in link mode, it is required only for the sending end of the link).
#	There are separate cycle properties for read and write blocks.  write_cycle_def controls
#	the write soft cycle, and read_cycle_def controls reads.  Setting either to 1 will cause a
#	soft cycle pulse to be issued at the start of EACH corresponding DR11 block.
#
write_cycle_def=1;
read_cycle_def=0;
#
#	Link mode also requires that the driver issue an ACLO FCN2 pulse (which becomes an ATTENTION
#	at the other end of the link) at the start of each DR11 read block.  This is selected by
#	setting the read_acf2_def property to 1.  We will default to 0 for now - to stay consistent with
#	the Sbus version of the driver.
#
read_acf2_def=0;
#
#	Several properties set the default states of the DR11 function bits, FCN3, FCN2, and FCN1.
#	This is done separately for read and write blocks, and when the device is opened
#	Each function bit has a separate property for each situation.  The names are
#	(hopefully) self-explanatory.  Permitted values are 0 or 1.
#
open_f3_def=0;
open_f2_def=0;
open_f1_def=0;
#
write_f3_def=1;
write_f2_def=0;
write_f1_def=0;
#
read_f3_def=1;
read_f2_def=0;
read_f1_def=1;
#
#	The maximum buffer size passed to our strategy routine is controlled by our IDR_MAXPHYS value
#	(set in idr_io.h) and the system's minphys routine.  Any user buffer larger than the smaller
#	of these values will be broken into chunks, and transferred via multiple calls to strategy.
#	There may be cases where ignoring the system's minphys is appropriate - in which case IDR_MAXPHYS
#	will rule.  IDR_MAXPHYS must not be changed - it matches the maximum size of our dma range counter.
#
#	To ignore the system minphys, set ignore_minphys to 1.
#
ignore_minphys=0;
#
#	END OF USER-CONFIGURABLE DEFAULTS
#
#
#
#	We force the interrupt priority of the
#	driver to level 9 to get it below the level of the
#	scheduler - the board's eeprom was reporting a class code that
#	caused the OBP to set the board's priority to the same level
#	as the scheduler, which required using a high-level
#	interrupt handler.
#
#	That should have been OK, but when two boards were running at the 
#	same time, LBOLT was getting confused and confusing the software timer.
#	It is not clear who was causing the problem.
#
#	We can solve the problem by changing our eeprom to give a class code
#	of 0x07, which currently gives us a priority of 1, but that seems
#	like too low a priority.
#
#	For now, we will force a relatively high priority, but below
#	the scheduler priority of 10.
#
#	DO NOT MODIFY THIS PROPERTY!!!!!
#
interrupt-priorities=9;