/* * idr_var.h * structure and "software" macro definition file for Linux 2.6.x driver for PCI DR11 boards * * Tahoma Technology * (formerly Ikon Corporation) * 107 2nd Avenue North * Seattle, WA, USA 98109 * * 206.728.6465 * http://www.tahomatech.com * tahoma@tahomatech.com * * * This code released under the GPL, and in the public domain * References to IKON left in place for compatibility and historical reasons */ #ifndef IDR_VAR_H #define IDR_VAR_H /* * nasty version detection - 2.6.18 and later, UTS_RELEASE is in utsrelease.h * not version.h so include utsrelease.h */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) #include #endif /* * conditional variable and mutex typedefs */ typedef struct { spinlock_t spin; long flags; } idr_mutex_t; typedef struct { wait_queue_head_t queue; } idr_cond_t; enum { IDR_COND_WAIT_SUCCESS, IDR_COND_WAIT_SIGNAL, IDR_COND_WAIT_TIMEOUT }; /* * unit structure for boards */ struct idr_unit_t { u_int instance; /* equivalent to minor number & board number */ idr_mutex_t mutex; /* used w/cond var to sleep (SMP compatibility) */ idr_cond_t cond; /* cond var used w/mutex */ volatile int sleeping; /* 1 if sleeping (helps detect timeout) */ struct pci_dev *pci_dev_p; /* handle for this board's pci dev structure */ void *plx_page_base_p; /* virtual address of plx reg page base */ void *idr_page_base_p; /* virtual address of idr reg page base */ volatile void *plx_base_p; /* virtual address of plx regs (avoid optimizer)*/ volatile void *idr_base_p; /* virtual address of idr regs (avoid optimizer)*/ void *iopb_base_p; /* virtual add of start of io parameter blocks */ int nr_iopbs; /* number of iopbs */ struct scatterlist *sg_list_p; /* points to scatterlist (for DMA mappings) */ dma_addr_t dma_handle; /* contains bus address of start of iopbs */ struct page **maplist_p; /* ptr to array of ptrs to page structs */ char *maplist_user_buf_p; /* ptr to current user buffer (or portion of) */ int maplist_nr_pages; /* number of pages in maplist */ int maplist_offset; /* offset from base of buffer */ int maplist_length; /* number of bytes in buffer */ int maplist_rw_mode; /* READ or WRITE */ char *dma_copy_buf_p; /* ptr to copy buffer or NULL */ volatile u_int unit_open; /* 1 = open */ spinlock_t open_lock; /* protect open flag from contention */ volatile u_int unit_attached; /* 1 = attached */ u32 unit_flags; /* our flag bits here */ u_int dma_time; /* dma timeout # in secs */ u_int attn_time; /* attention wait timeout # */ u_int rdy_time; /* ready wait timeout # */ u32 read_fcn; /* use at read start */ u32 write_fcn; /* use at write start */ u32 read_pulse; /* pulse at read start */ u32 write_pulse; /* pulse at write start */ u32 dev_and_vendor_id; /* device and vendor id from config regs */ u32 revision_id; /* revision id from config regs */ u_int range_resid; /* remaining count to xfer */ /* may be used for multi-dma */ /* per dr11 blocks (unused?) */ u_int dma_time_def; /* default dma wait - IN SECONDS */ u_int attn_time_def; /* default attn wait - IN SECONDS */ u_int rdy_time_def; /* default rdy wait - IN SECONDS */ u32 read_fcn_def; /* read fcn default */ u32 write_fcn_def; /* write fcn default */ u32 read_pulse_def; /* read pulse default */ u32 write_pulse_def; /* write pulse default */ u32 endian_def; /* endian default */ u32 latch_reg_def; /* latched functions default */ u32 mode_reg_def; /* mode register default */ u_char int_level; /* int level read from config register */ u_char pci_dev_int_level; /* (possibly) mapped int level */ char minor_node_name[16]; /* will contain this board's node name */ }; /* * "software" macro definitions */ /* * debug print macros - expand to nothing unless IDR_DEBUG is defined * DPRINT: print module and subroutine name and arg string + args w/a \n * DPRINTI: same, but include instance number * DPRINTC: continuation line same, but starts w/8 spaces and no instance */ #ifdef IDR_DEBUG #define DPRINT(format,args...) printk(KERN_DEBUG "idr: %s: " format "\n",\ __FUNCTION__ , ##args) #define DPRINTI(format,args...) printk(KERN_DEBUG "idr: %s: instance: %d: " format "\n",\ __FUNCTION__, instance , ##args) #else #define DPRINT(format,args...) #define DPRINTI(format,args...) #endif /* * info, error and warning printks like the above */ #define IPRINT(format,args...) printk(KERN_INFO "idr: %s: " format "\n",\ __FUNCTION__ , ##args) #define IPRINTI(format,args...) printk(KERN_INFO "idr: %s: instance: %d: " format "\n",\ __FUNCTION__, instance , ##args) #define EPRINT(format,args...) printk(KERN_ERR "idr: %s: " format "\n",\ __FUNCTION__ , ##args) #define EPRINTI(format,args...) printk(KERN_ERR "idr: %s: instance: %d: " format "\n",\ __FUNCTION__, instance , ##args) #define WPRINT(format,args...) printk(KERN_WARNING "idr: %s: " format "\n",\ __FUNCTION__ , ##args) #define WPRINTI(format,args...) printk(KERN_WARNING "idr: %s: instance: %d: " format "\n",\ __FUNCTION__, instance , ##args) /* * if user dma mode is permitted by install script (AUTO) and kernel * is not configured for more than 4G RAM (???), use direct user buffer dma. * otherwise use a copy buffer */ #if defined(CONFIG_HIGHMEM64G) || defined(IDR_DMA_MODE_COPY) #define IDR_COPY_BUF 1 #define IDR_DMA_MODE_MSG "user buffer DMA disabled, copy buffer in use" #else #define IDR_COPY_BUF 0 #define IDR_DMA_MODE_MSG "user buffer DMA enabled" #endif /* * deal with both old and new request_irq flags */ #ifndef IRQF_SHARED #define IRQF_SHARED SA_SHIRQ #endif /* * old and new ioctl entry points */ #ifdef HAVE_UNLOCKED_IOCTL #define IDR_UNLOCKED_IOCTL unlocked_ioctl:idr_new_ioctl, #else #define IDR_UNLOCKED_IOCTL #endif #ifdef HAVE_COMPAT_IOCTL #define IDR_COMPAT_IOCTL compat_ioctl:idr_new_ioctl, #else #define IDR_COMPAT_IOCTL #endif /* * another ugly version test * pt_regs arg to irq_handler being dropped in 2.6.19 * try to stay source compaible across kernels * IDR__PT_REGS should be defined as in 2.6.19 and later */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) #define IDR__PT_REGS #else #define IDR__PT_REGS , struct pt_regs *regs #endif /* * and yet _another_ ugly version test to determine how to access * the scatter/gather list */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) #define IDR_SET_PAGE(sg_p, page_p, len, off) \ sg_set_page(sg_p, page_p, len, off) #else #define IDR_SET_PAGE(sg_p, page_p, len, off) \ do {\ sg_p->page = page_p;\ sg_p->length = len;\ sg_p->offset = off;\ } while(0) #endif /* * macro definitions for memory mapped board register access * and io control block memory access * * these are gathered here to try to allow for easy portability to * arch's other than i386, where access to Pci board registers, and * the board's access to DMA chain list memory may be byte swizzled * * the PLXx macors are used to access plx registers directly * the IPLXx macors are used to access the plx dma registers via idr space - * which is necessary with early revs of the plx chip - we could use the IDRx macros * to do this, but IPLX should be more readable, and it will be easier to find them * to mod later if necessary for some future rev of the chip * * the configuration accesses will be done explicitly, without macros * * unit_p->xxx_base is defined as a pointer to a 32 bit value, offsets are byte offsets, so /4 * we could also do things with fancy casts * * offset to IOPB_XXXX will be iopb # * IOPB_SIZE + byte offset within the iopb so also /4 * * the previous driver version used direct pointer dereferencing (OK on x86) * we leave the pointer math as it was rather than try to cast the bases as u_ints or ? * to try to avoid future 64 bit pointer issues */ #define PLX_GETL(offset) readl(unit_p->plx_base_p + offset) #define PLX_PUTL(offset,value) writel(value, unit_p->plx_base_p + offset) #define IPLX_GETL(offset) readl(unit_p->idr_base_p + offset) #define IPLX_PUTL(offset,value) writel(value, unit_p->idr_base_p + offset) #define IDR_GETL(offset) readl(unit_p->idr_base_p + offset) #define IDR_PUTL(offset,value) writel(value, unit_p->idr_base_p + offset) #define IOPB_GETL(offset) readl(unit_p->iopb_base_p + offset) #define IOPB_PUTL(offset,value) writel(value, unit_p->iopb_base_p + offset) #endif /* IDR_VAR_H */