/* * idr_reg.h * Register definition file for Linux driver for PCI DR11 boards * * Tahoma Technology * (formerly Ikon Corporation) * 107 2nd Avenue North * Seattle, WA, USA 98109 * * 206.728.6465 * http://www.tahomatech.com * tahoma@tahomatech.com * * * This code released under the GPL, and in the public domain * References to IKON left in place for compatibility and historical reasons */ #ifndef _IDR_REG_H #define _IDR_REG_H /* * * IKON's PCI DR11-W emulators include the following: * * Model 10116 full size card * Model 10118 half size card * * The boards share a common register set, and operate under * the same software driver. The boards have almost identical features - * the driver will verify that a particular board supports a requested function. * * In particular, the 10118 does not have local memory for dma chain lists, and may in some * versions use DMA channel 1, rather than dma channel 0 * * All boards use some version of PLX technology's 9060 or 9080 PCI interface chip. Various * version of this chip determine the exact DMA setup requirements for the board. Some versions * support chaining DMA from local memory only, some support chaining lists in PCI memory, * and some implement DMA channel 1 only (channel 0 is used in most versions of the board). * Some versions of the chip require that we access the dma registers via a window in * the idr address range, and some require direct access via the plx address range. * * * There are three address ranges supported (and required) by the hardcopy boards: * configuration space, PLX register space, and IDR register space. The board's registers * are accesses through various ddi_... functions, which take an address as one of the arguments. * We will access the registers using defined offsets from the appropriate address range * base addresses. Macros will be used to shorten the typing task somewhat. * */ /* * the configuration space offsets and bit definitions are * provided in pci.h */ /* * plx run-time register offsets - when accessed directly via the * plx address range */ #define PLX_ENDIAN_REG 0x0C /* endian control (local config reg) 9080 ONLY */ #define PLX_ADD_0_ROM_DESC 0x18 /* add space 0/rom descriptor register */ #define PLX_MBX_0 0x40 /* mailbox registers */ #define PLX_MBX_1 0x44 #define PLX_MBX_2 0x48 #define PLX_MBX_3 0x4C #define PLX_MBX_4 0x50 #define PLX_MBX_5 0x54 #define PLX_MBX_6 0x58 #define PLX_MBX_7 0x5C #define PLX_PTOL_BELL 0x60 /* doorbell regsiters */ #define PLX_LTOP_BELL 0x64 #define PLX_INT_CSTAT 0x68 /* interrupt control/status regsiter */ #define PLX_EEPROM_USER 0x6C /* eeprom control and user bits */ #define PLX_DMA_MODE_0 0x80 /* dma channel 0 mode register */ #define PLX_DMA_PCI_ADD_0 0x84 /* pci address for dma transfer */ #define PLX_DMA_LOC_ADD_0 0x88 /* local address for dma transfer */ #define PLX_DMA_COUNT_0 0x8C /* dma transfer count in bytes */ #define PLX_DMA_DESC_PTR_0 0x90 /* dma descriptor pointer */ #define PLX_DMA_MODE_1 0x94 /* dma channel 1 mode register */ #define PLX_DMA_PCI_ADD_1 0x98 /* pci address for dma transfer */ #define PLX_DMA_LOC_ADD_1 0x9C /* local address for dma transfer */ #define PLX_DMA_COUNT_1 0xA0 /* dma transfer count in bytes */ #define PLX_DMA_DESC_PTR_1 0xA4 /* dma descriptor pointer */ #define PLX_DMA_CMD_STAT_BOTH 0xA8 /* dma command/status for both channels combined */ #define PLX_DMA_CMD_STAT_0 0xA8 /* dma command/status for channel 0 */ #define PLX_DMA_CMD_STAT_1 0xA9 /* dma command/status for channel 1 */ #define PLX_DMA_ARB_REG 0xAC /* local/dma arbitration register */ #define PLX_DMA_THRESH 0xB0 /* DMA threshold register */ /* * plx run-time register offsets when accesses via window * in idr address space */ #define IPLX_ENDIAN_REG 0x8C /* endian control (local config reg) 9080 ONLY */ #define IPLX_ADD_0_ROM_DESC 0x98 /* add space 0/rom descriptor register */ #define IPLX_MBX_0 0xC0 /* mailbox registers */ #define IPLX_MBX_1 0xC4 #define IPLX_MBX_2 0xC8 #define IPLX_MBX_3 0xCC #define IPLX_MBX_4 0xD0 #define IPLX_MBX_5 0xD4 #define IPLX_MBX_6 0xD8 #define IPLX_MBX_7 0xDC #define IPLX_PTOL_BELL 0xE0 /* doorbell regsiters */ #define IPLX_LTOP_BELL 0xE4 #define IPLX_INT_CSTAT 0xE8 /* interrupt control/status regsiter */ #define IPLX_EEPROM_USER 0xEC /* eeprom control and user bits */ #define IPLX_DMA_MODE_0 0x100 /* dma channel 0 mode register */ #define IPLX_DMA_PCI_ADD_0 0x104 /* pci address for dma transfer */ #define IPLX_DMA_LOC_ADD_0 0x108 /* local address for dma transfer */ #define IPLX_DMA_COUNT_0 0x10C /* dma transfer count in bytes */ #define IPLX_DMA_DESC_PTR_0 0x110 /* dma descriptor pointer */ #define IPLX_DMA_MODE_1 0x114 /* dma channel 1 mode register */ #define IPLX_DMA_PCI_ADD_1 0x118 /* pci address for dma transfer */ #define IPLX_DMA_LOC_ADD_1 0x11C /* local address for dma transfer */ #define IPLX_DMA_COUNT_1 0x120 /* dma transfer count in bytes */ #define IPLX_DMA_DESC_PTR_1 0x124 /* dma descriptor pointer */ #define IPLX_DMA_CMD_STAT_BOTH 0x128 /* dma command/status for both channels */ #define IPLX_DMA_CMD_STAT_0 0x128 /* individual dma cmd/stat offsets */ #define IPLX_DMA_CMD_STAT_1 0x129 #define IPLX_DMA_ARB_REG 0x12C /* local/dma arbitration register */ #define IPLX_DMA_THRESH 0x130 /* DMA threshold register */ /* * bit definitions for the PLX run-time registers */ /* * endian control register - 9080 ONLY */ #define CONFIG_BIG_ENDIAN 0x00000001 /* causes local accesses to config space to */ /* be big endian - NOT USED */ #define MASTER_BIG_ENDIAN 0x00000002 /* direct master big endian - NOT USED */ #define SLAVE_BIG_ENDIAN 0x00000004 /* direct slave access to idr space big endian */ #define SLAVE_ROM_BIG_ENDIAN 0x00000008 /* direct slave accesses to rom space big endian*/ /* - NOT USED */ #define BYTE_LANE_ENDIAN_MODE 0x00000010 /* causes upper word or byte to be used for */ /* access to 16 or 8 bit local bus */ #define SLAVE_1_BIG_ENDIAN 0x00000020 /* direct slave accesses to add space 1 big */ /* endian - NOT USED */ #define DMA_1_BIG_ENDIAN 0x00000040 /* dma channel 1 accesses big endian */ #define DMA_0_BIG_ENDIAN 0x00000080 /* dma channel 0 accesses big endian */ /* * address space 0/rom descriptor register * * for now, we only define the one bit we need */ #define ADD_0_PREFETCH_DISABLE 0x00000100 /* disable any prefetch reads to address space 0*/ /* * interrupt control/status register */ #define LSERR_ABORT_INT_ENABLE 0x00000001 /* enb local interrupt on target or master abort*/ #define LSERR_PARITY_INT_ENABLE 0x00000002 /* enable local interrupt on PCI parity error */ #define PCI_SERR 0x00000004 /* forces assertion of PCI SERR# signal */ #define MAILBOX_INT_ENABLE 0x00000008 /* enables local interrupt on mailbox write from*/ /* PCI 9080 ONLY */ #define DMA_0_INTERRUPT_SELECT 0x00000010 /* 1 causes dma 0 interrupt to assert PCI */ /* interrupt. 0 causes dma 0 interrupt to assert*/ /* local interrupt */ /* 9080 ONLY for other chips loop local out to */ /* local in on board */ #define DMA_1_INTERRUPT_SELECT 0x00000020 /* same as above - for dma channel 1 */ #define PCI_INTERRUPT_ENABLE 0x00000100 /* enables pci interrupts */ #define PCI_DB_INT_ENABLE 0x00000200 /* enables pci doorbell interrupts w/pci int */ /* enable */ #define PCI_ABORT_INT_ENABLE 0x00000400 /* enables pci interrupt on master or target */ /* abort w/pci int enb */ #define PCI_LOCAL_INT_ENABLE 0x00000800 /* enbles local interrupt to cause pci interrupt*/ /* w/pci int enb */ #define RETRY_ABORT_ENABLE 0x00001000 /* 256 consecutive master retries will cause */ /* target abort */ #define PCI_DB_INTERRUPT 0x00002000 /* 1 indicates pci doorbell interrupt is active */ #define PCI_ABORT_INTERRUPT 0x00004000 /* 1 indicates pci abort interrupt is active */ #define LOCAL_INTERRUPT 0x00008000 /* 1 indicates local interrupt is active */ #define LOCAL_INT_OUT_ENABLE 0x00010000 /* enables local interrupt output */ #define LOCAL_DOORBELL_INT_ENB 0x00020000 /* enables local doorbell interrupts w/local int*/ /* enb */ #define LOCAL_DMA_0_INT_ENABLE 0x00040000 /* enables dma chan 0 local interrupt w/local */ /* int enb */ #define LOCAL_DMA_1_INT_ENABLE 0x00080000 /* enables dma chan 1 local interrupt w/local */ /* int enb */ #define LOCAL_DB_INTERRRUPT 0x00100000 /* 1 indicates local doorbell interrupt is */ /* active */ #define DMA_0_INTERRUPT 0x00200000 /* 1 indicates dma channel 0 interrupt is */ /* active */ #define DMA_1_INTERRUPT 0x00400000 /* 1 indicates dma channel 1 interrupt is active*/ #define BIST_INTERRUPT 0x00800000 /* 1 indicates that bilt in self test int is */ /* active */ #define DIRECT_MASTER_ABORT_FLAG 0x01000000 /* 1 indicates abort during direct */ /* master xfer */ #define DMA_0_ABORT_FLAG 0x02000000 /* 1 indicates abort during dma chan 0 xfer */ #define DMA_1_ABORT_FLAG 0x04000000 /* 1 indicates abort during dma chan 1 xfer */ #define RETRY_ABORT_FLAG 0x08000000 /* 1 indicates abort after 256 retries */ #define MBX_0_FLAG 0x10000000 /* 1 indicates PCI wrote to mailbox 0 9080 ONLY */ #define MBX_1_FLAG 0x20000000 /* 1 indicates PCI wrote to mailbox 1 9080 ONLY */ #define MBX_2_FLAG 0x40000000 /* 1 indicates PCI wrote to mailbox 2 9080 ONLY */ #define MBX_3_FLAG 0x80000000 /* 1 indicates PCI wrote to mailbox 3 9080 ONLY */ /* * eeprom control, pci command codes, user bits, init control */ #define DMA_READ_CMD_MASK 0x0000000F /* masks bits used as pci command during dma */ /* read */ #define DMA_READ_CMD_DEF 0x0000000E /* power up default for dma reads */ #define DMA_WRITE_CMD_MASK 0x000000F0 /* masks bits used as pci command during dma */ /* write */ #define DMA_WRITE_CMD_DEF 0x00000070 /* power up default for dma writes */ #define MASTER_READ_CMD_MASK 0x00000F00 /* masks bits used as pci command during direct */ /* master read */ #define MASTER_READ_CMD_DEF 0x00000600 /* power up default for direct master reads */ #define MASTER_WRITE_CMD_MASK 0x0000F000 /* masks bits used as pci command during direct */ /* master write */ #define MASTER_WRITE_CMD_DEF 0x00007000 /* power up default for direct master writes */ #define USER_OUTPUT 0x00010000 /* user output bit */ #define USER_INPUT 0x00020000 /* user input bit */ #define EEPROM_CLOCK 0x01000000 /* toggling this bit generates an eeprom clock */ #define EEPROM_CHIP_SELECT 0x02000000 /* drives the eeprom chip select */ #define EEPROM_WRITE_BIT 0x04000000 /* write bit to eeprom */ #define EEPROM_READ_BIT 0x08000000 /* read bit from eeprom */ #define EEPROM_PRESENT 0x10000000 /* 1 indicates that an eeprom is present */ #define CONFIGURATION_RELOAD 0x20000000 /* 0-to-1 causes reload of configuration */ /* registers from eeprom */ #define PLX_SOFT_RESET 0x40000000 /* holds plx chip reset and aserts local reset */ /* out (big hammer!) */ #define LOCAL_INIT_DONE 0x80000000 /* local init done - since no local master - */ /* this is held at 1 by #NB pin */ /* * dma channels 0 and 1 mode register bits */ #define DMA_BUS_WIDTH_MASK 0x00000003 /* mask for dma local bus width bits */ #define DMA_BUS_8_BIT 0x00000000 /* 8 bit dma bus */ #define DMA_BUS_16_BIT 0x00000001 /* 16 bit dma bus */ #define DMA_BUS_32_BIT 0x00000002 /* 32 bit dma bus */ #define DMA_WAIT_STATE_MASK 0x0000003C /* mask for local bus wait state count */ #define DMA_WAIT_1 0x00000004 /* one wait state used for current boards */ #define DMA_READY_IN_ENABLE 0x00000040 /* enable ready input during dma */ #define DMA_BTERM_IN_ENABLE 0x00000080 /* enable bterm input during dma */ #define DMA_BURST_ENABLE 0x00000100 /* enable local bursting during dma */ #define DMA_CHAIN_ENABLE 0x00000200 /* enable dma chaining */ #define DMA_DONE_INTERRUPT_ENB 0x00000400 /* enable dma done interrupt */ #define DMA_LOCAL_ADD_HOLD 0x00000800 /* 0 causes local add to increment during dma */ #define DMA_DEMAND_MODE 0x00001000 /* enables demand mode dma (DREQ# input) */ #define DMA_WRITE_INVALID 0x00002000 /* perform write and invalidate cycles 9080 ONLY */ #define DMA_EOT_ENABLE 0x00004000 /* enable eot input 9060SD and 9080 only */ #define DMA_STOP_MODE 0x00008000 /* 0=blast terminates xfer, 1=eot on, */ /* or dreq off in demand mode terminates 9060SD */ /* and 9080 ONLY */ #define DMA_CLEAR_COUNT_MODE 0x00010000 /* causes byte count in each descriptor to be */ /* zeroed when done 9080 ONLY */ /* * dma pci address registers, local address registers, and * transfer size registers have no special control bits * * transfer count register is limited to lower 23 bits * =8Mbyte max xfer per chain list element */ #define DMA_XFER_COUNT_MASK 0x007fffff /* * dma channels 0 and 1 descriptor pointer register bits */ #define DMA_CHAIN_IN_PCI_MEM 0x00000001 /* if set, dma chain list in pci memory, */ /* otherwise local memory */ /* some boards do not have local memory */ #define DMA_END_OF_CHAIN 0x00000002 /* if set, this chain element is last in list */ #define DMA_LINK_INTERRUPT 0x00000004 /* if set, interrupt when this element's count */ /* is exhausted */ #define DMA_INPUT 0x00000008 /* if set, direction of xfer is local to PCI*/ #define DMA_NEXT_ADDRESS_MASK 0xfffffff0 /* bit mask for address of next quad word list */ /* element */ /* * dma channels 0 and 1 have identical BYTE wide command/status registers * which may be accessed at separate byte addresses, or as a single 16 or 32 * bit register * * dma channel 0 is at the lower offset, channel 1 is the next higher byte offset * * the following defines assume that both registers are accessed at the same time * as a 16 or 32 bit value * * if for some reason it is necessary to do an access to a single byte-wide register, * the DMA_0... defines should be used for both registers (and obviously getb and * putb should be used */ #define DMA_0_ENABLE 0x01 /* enables the dma channel when 1 - disables (pauses) */ /* when 0 */ #define DMA_0_START 0x02 /* 1 starts the dma transfer if enable true */ #define DMA_0_ABORT 0x04 /* 1 aborts the transfer, leaves enable true */ #define DMA_0_CLEAR_INTERRUPT 0x08 /* 1 clears the dma interrupt */ #define DMA_0_DONE 0x10 /* 1 indicates that the dma transfer is complete */ #define DMA_1_ENABLE 0x0100 #define DMA_1_START 0x0200 #define DMA_1_ABORT 0x0400 #define DMA_1_CLEAR_INTERRUPT 0x0800 #define DMA_1_DONE 0x1000 /* * dma arbitration and threshold registers left at * default of 0 for current board implementations */ /* * idr (ikon logic portion of board) register offsets * registers are byte wide in low byte of 32 bit longword * * all idr registers may be accessed as 32 bit values */ #define IDR_LATCHED_FUNCTIONS 0x00 /* (read/write) latched function and mask bits */ #define IDR_116_PULSES 0x04 /* (write) internal pulses */ #define IDR_FLAGS 0x04 /* (read) flag bits */ #define IDR_DEVICE_PULSES 0x08 /* (write) external pulses */ #define IDR_STATUS 0x08 /* (read) status bits */ #define IDR_MODE 0x0C /* (read/write) mode control bits */ #define IDR_RANGE_LOW 0x10 /* (read/write) range register low 8 bits */ #define IDR_RANGE_MID 0x14 /* (read/write) range register mid 8 bits */ #define IDR_RANGE_HIGH 0x18 /* (read/write) range register high 8 bits */ #define IDR_FIFO_STATUS 0x1C /* (read) fifo status bits */ #define IDR_DATA_OUT 0x40 /* (write) p-i/o data to device */ #define IDR_DATA_IN 0x40 /* (read) p-i/o data from device */ #define IDR_PLX_READBACK 0x60 /* (read) not used w/current boards */ #define IDR_PLX_RUNTIME_BASE 0x80 /* base of plx window in idr address range */ #define IDR_MEMORY_BASE 0x140 /* base of local memory (some models) */ /* * bit definitions for the ikon (idr) regsiters */ /* * latched function register bits */ #define END_OF_RANGE_INT_ENB 0x80 /* end of range interrupt mask */ #define ATTENTION_INT_ENB 0x40 /* attention interrupt mask */ #define IDR_DMA_ENABLE 0x20 /* enable idr logic to rq dma transfers */ #define DMA_INPUT_MODE 0x10 /* 1 = dma input to memory, 0 = output */ #define FUNCTION_MASK 0x0E /* mask for function bits */ #define FUNCTION_3 0x08 /* function bits */ #define FUNCTION_2 0x04 #define FUNCTION_1 0x02 /* * 116 pulse register bit definitions */ #define RESET_EOR_FLAG 0x80 /* resets end of range flag */ #define RESET_ATTENTION_FLAG 0x40 /* resets attention flag */ #define RESET_ERROR_FLAGS 0x20 /* resets parity and multi-cycle error flags */ #define MASTER_CLEAR 0x10 /* resets the idr logic (not plx or device) */ #define CLEAR_OUTPUT_FIFO 0x08 /* resets the output fifo */ #define CLEAR_INPUT_FIFO 0x04 /* resets the input fifo */ #define READ_OUTPUT_FIFO 0x02 /* moves 16 bit word from fifo to output latches */ #define WRITE_INPUT_FIFO 0x01 /* moves 16 bit word from input to input fifo */ /* * flags register bit definitions */ #define END_OF_RANGE_FLAG 0x80 /* sets at idr counter underflow (not dma ctr) */ #define ATTENTION_FLAG 0x40 /* sets when attention goes true (edge) */ #define PARITY_ERROR_FLAG 0x20 /* sets w/ dma or p-i/o parity error */ #define MULTI_CYCLE_ERROR_FLAG 0x10 /* sets if multi-cycle cycle request error */ /* * device pulses register bit definitions */ #define SET_READY 0x80 /* forces ready and drains input fifo if input */ #define DEVICE_INIT 0x10 /* pulses init line to device */ #define ACLO_FCN_2 0x04 /* pulses aclo fnct2 line to device */ #define SOFT_CYCLE 0x02 /* forces cycle request */ #define GO 0x01 /* pulses go to device and enables block xfer */ /* * status register bit definitions */ #define READY 0x80 /* ready for another command or block xfer */ #define ATTENTION 0x40 /* attention input - not latched */ #define STATUS_MASK 0x0E /* mask for device status bits */ #define STATUS_A 0x08 /* status bits from device */ #define STATUS_B 0x04 #define STATUS_C 0x02 #define A00_INPUT 0x01 /* a00 input from device */ /* * mode register bit definitions */ #define LONG_READY 0x80 /* 1 = ready true at busy t.e 0 = ready true */ /* during busy */ #define DISABLE_RANGE 0x40 /* 1 disables dr11 range counter */ #define DISABLE_CRQ_B 0x20 /* 1 disables crq b input */ #define CYCLE_POLARITY 0x08 /* 0 = crq rising active, 1 = falling active */ #define BUSY_POLARITY 0x04 /* 0 = busy low true, 1 = high true */ #define TIMING_MASK 0x03 /* mask for handshake timing bits */ #define SPEED_3 0x03 /* slowest speed */ #define SPEED_2 0x02 #define SPEED_1 0x01 #define SPEED_0 0x00 /* * fifo status register bit definitions */ #define OUTPUT_FIFO_FULL 0x80 /* fifo status bits */ #define OUTPUT_FIFO_HALF_FULL 0x40 #define OUTPUT_FIFO_EMPTY 0x20 #define INPUT_FIFO_FULL 0x08 #define INPUT_FIFO_HALF_FULL 0x04 #define INPUT_FIFO_EMPTY 0x02 /* * other useful definitions */ /* * define max DR11 counter size */ #define IDR_DR11_MAXBLOCK 0xFFFFFF #define IKON_VENDOR_ID 0x11d5 /* our pci vendor id */ #define IDR_DEVICE_ID_LIST 0x0116,0x0118 /* supported board IDs */ #define PLX_REG_SIZE 0x100 /* size of plx 9080 register set */ #define IDR_REG_SIZE 0x2000 /* size of ikon register set */ /* * mask for revision id portion of class code & rev id config longword */ #define REV_ID_MASK 0xFF /* * we are 32 bit DMA capable */ #define IDR_DMA_MASK 0xffffffff /* * define size of i/o parameter block (link of dma chain list) * and the offsets of elements of the block from the base address */ #define IOPB_SIZE 0x10 /* 16 bytes per block */ #define IOPB_PCI_ADDRESS 0x00 /* starting pci address of user buffer block */ #define IOPB_LOCAL_ADDRESS 0x04 /* starting local address */ #define IOPB_TRANSFER_SIZE 0x08 /* number of bytes in this block */ #define IOPB_NEXT_IOPB 0x0c /* physical address of next iopb in list */ #endif /* IDR_REG_H */