/* * idr_io.h * public ioctl and default definition file for Linux 2.0.35 driver for * PCI DR11 boards * * (this file unchanged through 2.6.x versions of driver) * * Tahoma Technology * (formerly Ikon Corporation) * 107 2nd Avenue North * Seattle, WA, USA 98109 * * 206.728.6465 * http://www.tahomatech.com * tahoma@tahomatech.com * * This code released under the GPL, and in the public domain * References to IKON left in place for compatibility and historical reasons */ #ifndef IDR_IO_H #define IDR_IO_H /* * this file is to be #include(d) in the program that calls the 10118 driver. * it is also used internally by the driver - don't modify this unless * you know what you are doing!!!! * * the PCI driver attempts to maintain ioctl command and argument compatibility * with the Sbus SunOS and Solaris drivers, and the Solaris Pci driver. * Some Sbus ioctls used the Sbus register include file * for the bit definitions of arguments. this driver will move those old compatibility * definitions into this _io.h file as sub-defines to command defines. * * including this file in the calling program will also cause idr_reg.h to be included. * this makes register bit defines available - to be used in the ioctls that access * and report the state of the pci board's registers. see idr_reg.h for bit definitions. * * some new ioctls are added to allow direct access to new registers, and to PCI * configuration data that wasn't available in the Sbus version */ #include #include /* * pick up register definitions for use by calling program - if not already included */ #ifndef _IDR_REG_H #include "./idr_reg.h" #endif /* the ioctl() function call looks like: * * ioctl(filedescriptor,command,argument) * * argument is used in some of the idr ioctl calls to provide values to * the driver ioctl routine, or return values to the calling program. * the argument is restricted to a maximum of 255 * bytes - by unix, and by the driver. * * the following ioctl commands * are available to programs using the idr driver: * * IDRIO_SET_MODE sets the mode register bits and the RDIS bit in * the latched functions register - Sbus compatibility * IDRIO_IMM_FCN sets the function bits immediately * IRDIO_READ_FCN sets the function bits before each block read * IDRIO_WRITE_FCN sets the function bits before each block write * IDRIO_IMM_PULSE issues pulse commands immediately * IDRIO_READ_PULSE issues pulse commands at each block read * IDRIO_WRITE_PULSE issues pulse commands at each block write * IDRIO_SET_DMA_TIME sets dma timeout value * IDRIO_SET_ATTN_TIME sets wait for attention timeout value * IDRIO_SET_RDY_TIME sets wait for ready timeout value * IDRIO_ATTN_WAIT waits for attention 0-to-1 transition * IDRIO_RDY_WAIT waits for READY * IDRIO_GET_STATUS gets flags/status register - Sbus compatibility * IDRIO_GET_RANGE gets range counter value * IDRIO_GET_REGS gets all registers including PLX chip's * note that latch reg bit DMIN is forced to 1 by * this ioctl(to allow reading data in reg) * IDRIO_GET_FLAGS returns various driver flag and error bits - Sbus compatibility * IDRIO_DATA_OUT writes 16 bits to DR11 output latches * IDRIO_DATA_IN reads 16 bits from DR11 input latches * IDRIO_SET_RANGE sets DR11 range counter in manual mode * IDRIO_AUTO selects auto mode (default). auto mode causes DR11 * range & controls to be set up for each read/write * call at same time as DMA logic is set up. DMA and * DR11 blocks are set to the same size, and a single * DMA block is used per DR11 block. in auto mode, all * that is necessary to do dma transfers is read or write * calls. * IDRIO_MANUAL selects manual mode. manual mode causes read/write * calls to set up DMA controller only. DR11 range * and controls must be set up explicitly by calling pgm. * manual mode allows multiple read/write calls per DR11 * block, or disabling the DR11 range counter and doing * continuous transfers. * IDRIO_START_READ * IDRIO_START_WRITE in manual mode, enables overall block-issued before * DR11 logic is enabled with GO command. and before the * first unix read or write call. * IDRIO_BLOCK_END in manual mode, disables overall block transfer-issued * after all DR11 transfers are complete, typically after * a wait for ready has returned successfully. * * *** new ioctl commands for PCI DR11-W emulators *** * * IDRIO_DEV_AND_VEND_ID return board device and vendor ids in arg * IDRIO_REVISION_ID return board revision level in arg * IDRIO_SET_NEW_MODE set PCI DR11 mode * IDRIO_GET_NEW_STATUS get PCI device status * IDRIO_GET_NEW_FLAGS get PCI flag bits * IDRIO_MASTER_CLEAR reset board - use only in dire emergencies! * */ /* the ioctl command codes conform to the unix pattern: * * the top 3 bits of the 32 bit value indicate whether arguments * are to be copied in, copied out, both, or neither. * * 0x80000000 = copy in * 0x40000000 = copy out * 0x20000000 = no argument transfer * 0xC0000000 = copy in and out * * the number of bytes in the argument is encoded in the lower * 8 bits of the upper half of the u_int, and the actual command * is encoded in the lower half. a rather arbitrary character, * which is intended to identify the driver, is also encoded in * the lower half of the command. it becomes part of the command * value. * * for all commands the arg length is part of * the command value. * * commands which require arguments - in or out - will pass those * arguments as unsigned 32 bit integers via the arg pointer. * * * the magic character that identifies this driver is hereby * (arbitrarily) chosen to be 'D'. * * the following ioctl commands are defined using pre-existing * ioctl command macros. the CMD_MASK and COUNT_MASK values * defined MUST match the usage in ioccom.h. refer to that include * file for further information. */ /* * other versions of this driver used the entire lower 16 bits of the command to * decode the specific function requested. this includes both the ioctl type * (magic letter) and number as defined in linux/ioctl.h. we reconstruct the full * function mask the hard way to try to protect against the shifting sands of linux defines */ #define IDRIO_CMD_MASK ((_IOC_TYPEMASK << _IOC_TYPESHIFT) | (_IOC_NRMASK << _IOC_NRSHIFT)) #define IDRIO_COUNT_MASK IOCSIZE_MASK /* arg byte count here - IOCSIZE_MASK is */ /* already shifted left */ /* * THE SOLARIS 2.0 MACROS IN ioccom.h WANT THE 'MAGIC LETTER' QUOTED. * THE SOLARIS 1.X MACROS WANTED IT WITHOUT QUOTES. * LINUX WANTS QUOTES * * SOME VERSIONS OF ioccom.h DIDN'T INCLUDE _IORN AND _IOWN. SOL2 SEEMS TO HAVE THEM * linux/ioctl.h DOESN'T SEEM TO HAVE THEM * * we will use the lower-level _IOC macro (asm/ioctl.h) to define these since we need to * provide the size as an actual byte count, not as a type input to sizeof(), which is used * by the higher level (_IOR, _IOW) macros */ #define _IORN(type, nr, size) _IOC(_IOC_READ, (type), (nr), (size)) #define _IOWN(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (size)) #define IDRIO_SET_MODE _IOW('D',1,__u32) /* set mode reg bits & RDIS */ /* inlatched reg */ /* Sbus compatibility ioctl - define old bits */ #define IDR_RDYT 0x80 /* long ready timing */ #define IDR_FMOD 0x40 /* not used in pci version */ #define IDR_BDIS 0x20 /* disable cycle req b */ #define IDR_SWAP 0x10 /* byte swap - not currently supported in pci */ #define IDR_CRQP 0x08 /* selects crq falling edge active */ #define IDR_BSYP 0x04 /* selects busy active high */ #define IDR_SPEED_MASK 0x03 /* two bits select handshake speed */ #define IDR_SPD_0 0x00 /* fastest timing */ #define IDR_SPD_1 0x01 #define IDR_SPD_2 0x02 #define IDR_SPD_3 0x03 #define IDR_RDISX 0x2000 /* disable range counter */ #define IDRIO_IMM_FCN _IOW('D',2,__u32) /* set function bits NOW - immediate */ /* write to fcn bits */ /* define old bits for Sbus driver compatibility */ #define IDR_FCN3 0x08 /* function bits */ #define IDR_FCN2 0x04 #define IDR_FCN1 0x02 #define IDR_FMASK 0x0E /* all function bits */ #define IDRIO_READ_FCN _IOW('D',3,__u32) /* set fcn bits at read start - fcn write */ /* deferred until */ /* following (and all later) read calls */ #define IDRIO_WRITE_FCN _IOW('D',4,__u32) /* set fcn bits at write time - as in read_fcn */ /* above */ #define IDRIO_IMM_PULSE _IOW('D',5,__u32) /* issue pulses NOW - immediate write to pulse */ /* reg. masked to allow only device pulses */ /* define old bits for Sbus driver compatibility*/ #define IDR_RATN 0x40 /* clear attention flag */ #define IDR_TERM 0x20 /* set ready true */ #define IDR_MCLR 0x10 /* master clear idr logic - NOT FOR FRIVOLOUS USE */ #define IDR_INIT 0x08 /* send init pulse to device */ #define IDR_ACF2 0x04 /* send acf2 pulse to device */ #define IDR_CYCL 0x02 /* force cycle */ #define IDR_GO 0x01 /* send go and enable dr11 transfers */ #define OLD_PULSE_MASK IDR_RATN | IDR_TERM | IDR_INIT | IDR_ACF2 | IDR_CYCL | IDR_GO #define IDRIO_READ_PULSE _IOW('D',6,__u32) /* issue pulses at read start - deferred*/ /* until next(and later) read calls */ #define IDRIO_WRITE_PULSE _IOW('D',7,__u32) /* issue pulses at write time - as in */ /* read_pulse above */ #define IDRIO_SET_DMA_TIME _IOW('D',8,__u32) /* DVMA block timeout in secs - also */ /* controls EOR timeout in auto mode */ /* manual eor timeout uses RDY_TIME */ #define IDRIO_SET_ATTN_TIME _IOW('D',9,__u32) /* ATTENTION wait timeout # */ #define IDRIO_SET_RDY_TIME _IOW('D',10,__u32) /* READY wait timeout in seconds */ #define IDRIO_ATTN_WAIT _IO('D',11) /* wait for ATTENTION flag */ #define IDRIO_RDY_WAIT _IO('D',12) /* wait for DR11 READY */ #define IDRIO_GET_STATUS _IOR('D',13,__u32) /* returns Sbus style DR11 status & */ /* flags reg */ /* Sbus compatibility ioctl - define old bits */ #define IDR_EORF 0x80 /* DR11 end-of-range flag */ #define IDR_ATTF 0x40 /* attention flag */ #define IDR_ATTN 0x20 /* actual attention signal */ #define IDR_MCER 0x10 /* multi-cycle error flag */ #define IDR_STAT_MASK 0x0E /* mask for device status bits */ #define IDR_STTA 0x08 /* status bits from device */ #define IDR_STTB 0x04 #define IDR_STTC 0x02 #define IDR_REDY 0x01 /* master DR11 ready bit (0=block xfer enabled) */ #define IDRIO_GET_RANGE _IOR('D',14,__u32) /* returns DR11 range register - gets */ /* actual register bits which are */ /* initially set to the WORD count */ /* minus 1 and decrement per DR11 16 */ /* bit transfer */ /* * return array size used here and in ioctl code * _IORN takes the direct byte count, not a type to be * passed to the sizeof() operator, as is done with * the other _IOx macros */ #define IDR_RETURN_ARRAY_SIZE 19 /* in __u32 words!! */ #define IDRIO_GET_REGS _IORN('D',15,IDR_RETURN_ARRAY_SIZE * 4) /* puts registers in arg */ /* * returns all "IDR" registers and some "PLX" registers. * also returns device IDs and revision level. * PLX registers are all 32 bits wide. DR11 registers are 8 * bits wide. except the data in register which is 16 bits wide. * each is returned in a 32 bit longword in as shown below. * the DMA registers returned are either channel 0 or 1, depending * on which is used in the particular revision of the board. * * (__u32 larg[19]) * * larg[0] = device ID (high 16 bits) & vendor ID (low 16 bits) * larg[1] = revision ID * larg[2] = PLX interrupt control/status * larg[3] = PLX EEPROM control and user bits * larg[4] = PLX DMA mode * larg[5] = PLX DMA PCI address * larg[6] = PLX DMA local address * larg[7] = PLX DMA transfer count * larg[8] = PLX DMA descriptor pointer * larg[9] = PLX DMA command/status register * larg[10] = latched functions * larg[11] = flags * larg[12] = status * larg[13] = mode * larg[14] = DR11 range counter low byte * larg[15] = DR11 range counter mid byte * larg[16] = DR11 range counter high byte * larg[17] = fifo status * larg[18] = data in * */ #define IDRIO_GET_FLAGS _IOR('D',16,__u32) /* returns driver unit_flags */ #define IDR_DVMA_WAIT 0x80000000 /* waiting for t/c */ #define IDR_EOR_WAIT 0x40000000 /* waiting for EOR */ #define IDR_ATTN_WAIT 0x20000000 /* waiting for attention */ #define IDR_RDY_WAIT 0x10000000 /* waiting for ready */ #define IDR_DVMA_TIMEOUT 0x08000000 /* dma wait timed out */ #define IDR_EOR_TIMEOUT 0x04000000 /* eor wait timeout */ #define IDR_ATTN_TIMEOUT 0x02000000 /* attn timeout */ #define IDR_RDY_TIMEOUT 0x01000000 /* ready wait timeout */ #define IDR_MANUAL 0x00800000 /* manual mode */ #define IDR_INPUT 0x00400000 /* used w/waiting-for */ /* indicates xfer dir */ #define IDR_MCYL_ERR 0x00200000 /* multicycle error */ #define IDR_SIG_RECEIVED 0x00100000 /* sleep term'd by signal */ #define IDR_PAR_ERR 0x00080000 /* DR11 parity error - new for pci */ /* * idr_clear_flags used to reset the above flags (INSIDE DRIVER ONLY!!!!!!) */ #define IDR_CLEAR_FLAGS ~(IDR_DVMA_WAIT|IDR_EOR_WAIT|IDR_ATTN_WAIT|\ IDR_RDY_WAIT|IDR_DVMA_TIMEOUT|IDR_EOR_TIMEOUT|IDR_ATTN_TIMEOUT|IDR_RDY_TIMEOUT\ |IDR_MCYL_ERR|IDR_SIG_RECEIVED|IDR_PAR_ERR) #define IDRIO_DATA_OUT _IOW('D',17,__u32) /* 16 bits to DR11 output reg */ #define IDRIO_DATA_IN _IOR('D',18,__u32) /* reads DR11 input reg */ #define IDRIO_SET_RANGE _IOW('D',19,__u32) /* sets DR11 range register to arg - */ /* arg should be */ /* desired WORD count minus 1 */ #define IDRIO_AUTO _IO('D',20) /* selects manual mode - auto is default */ #define IDRIO_MANUAL _IO('D',21) /* selects manual mode - manual requires direct */ /* control of DR11 range count and block start */ /* and end by user */ #define IDRIO_START_READ _IO('D',22) /* enables overall block xfer. manual mode only!*/ #define IDRIO_START_WRITE _IO('D',23) /* enables write block transfer */ #define IDRIO_BLOCK_END _IO('D',24) /* terminates block xfers - required in manual */ /* mode - not used in auto mode */ /* * start read or write enables the DR11 control logic. block end disables it * start read or write should be issued before the first unix read or write * call in manual mode. these ioctls do not issue a go or cycle pulse, that * must be done by the calling program AFTER the start ioctl. */ /* *** new ioctls for PCI DR11 *** */ #define IDRIO_DEV_AND_VEND_ID _IOR('D',25,__u32) /* returns device and vendor ids in arg */ /* vendor id is low 16 bits, device id */ /* is high 16 bits */ #define IDRIO_REVISION_ID _IOR('D',26,__u32) /* returns board revision level in arg */ #define IDRIO_SET_NEW_MODE _IOW('D',27,__u32) /* sets PCI DR11 mode */ #define IDRIO_GET_NEW_STATUS _IOR('D',28,__u32) /* gets PCI DR11 status register */ #define IDRIO_GET_NEW_FLAGS _IOR('D',29,__u32) /* gets PCI DR11 flags register */ #define IDRIO_MASTER_CLEAR _IO('D',30) /* full reset of board. emergencies only!*/ /* * define various flags and constants * * the _DEF defines may be modified by the user to change te module install time * configuration and operating behavior of the board(s) and driver. * at this time, these parameters apply to all boards operating under * a particular driver * * THESE DEFINES SHOULD NOT BE MODIFIED HERE - TYESE ARE THE DEFAULTS USED WHEN THERE * ARE NO OVERRIDING VALUES SUPPLIED TO insmod * IF IT IS NECESSARY TO CHANGE THE DEFAULT BEHAVIOR OF THE DRIVER, * MAKE CHANGES BY SUPPLYING APPROPRIATE VALUES TO insmod * * the values that may be modified at module install time are; * * speed_def handshake speed - 0=fastest, 3=slowest * dma_time_def dma timeout in seconds * attn_time_def attention timeout in seconds * rdy_time_def ready timeout in seconds * byte_swap_def 0=no swap, 1=swap * cycle_pol_def cycle polarity - 0=rising edge, 1=falling edge * busy_pol_def busy polarity - 0=asserted low, 1=asserted high * write_cycle_def write cycle - 1=issue soft cycle, 0=no soft cycle * read_cycle_def read cycle - 0=no soft cycle, 1=issue soft cycle * read_acf2_def acf2 pulse - 0=no pulse on read, 1=pulse on read * * **the function bits are listed separately for historical reasons** * * open_f3_def function 3 bit on open - 0=clear, 1=set * open_f2_def function 2 bit on open - 0=clear, 1=set * open_f1_def function 1 bit on open - 0=clear, 1=set * write_f3_def function 3 bit on write - 0=clear, 1=set * write_f2_def function 2 bit on write - 0=clear, 1=set * write_f1_def function 1 bit on write - 0=clear, 1=set * read_f3_def function 3 bit on read - 0=clear, 1=set * read_f2_def function 2 bit on read - 0=clear, 1=set * read_f1_def function 1 but on read - 0=clear, 1=set * * * max_phys_def maximum dma transfer (in k) * max_phys_def * 1024 is largest user buffer that * will be transferred in one chunk * larger buffers will be broken into max_phys_def * sized dma blocks * * example: /sbin/insmod idr_debug.o max_boards=3 * * the above loads the version of the driver with debug printing enabled, and probes for * a maximum of three boards */ #define DMA_TIME_MAX 600 /* protect against hanging if caller asks for giant # */ #define ATTN_TIME_MAX 600 #define RDY_TIME_MAX 600 #define DMA_TIME_MIN 10 /* try to prevent timeout during legit dma or wait */ #define ATTN_TIME_MIN 10 #define RDY_TIME_MIN 10 #define SPEED_DEF 0 /* handshake speed default */ #define DMA_TIME_DEF 30 /* dma time-out default seconds */ #define ATTN_TIME_DEF 30 /* fifo empty and <1/2 full time-out */ #define RDY_TIME_DEF 30 /* ready wait time default */ #define BYTE_SWAP_DEF 0 /* don't swap bytes (for SPARC, this means swap bytes) */ #define CYCLE_POL_DEF 0 /* cycle req rising edge active */ #define BUSY_POL_DEF 0 /* busy asserted low */ #define WRITE_CYCLE_DEF 1 /* issue soft cycle on write */ #define READ_CYCLE_DEF 0 /* not on read */ #define READ_ACF2_DEF 0 /* do not pulse aclo fcn2 on read (&never on write) */ #define OPEN_F3_DEF 0 /* function bit defaults for idr_open() time */ #define OPEN_F2_DEF 0 #define OPEN_F1_DEF 0 #define WRITE_F3_DEF 1 /* function bit defaults for write block */ #define WRITE_F2_DEF 0 #define WRITE_F1_DEF 0 #define READ_F3_DEF 1 /* function bit defaults for read block */ #define READ_F2_DEF 0 #define READ_F1_DEF 1 #define MAX_PHYS_ORDER_DEF 4 /* 2**max_phys_order * PAGE_SIZE = max dma xfer */ /* larger user buf is xferred in chunks */ /* 4 -> 64K max w/4K pages */ #define MAX_BOARDS_DEF 1 /* default to one board, to save a little kernel memory */ #endif /* IDR_IO_H */