/*	This file contains the internal definitions for the hp-x driver for
	IKON's ISA/EISA hardcopy boards.  It is used by all
	copies of the driver.  Differences between multiple copeis of the driver
	(required when multiple boards are installed) are defined in the code modules.
*/

/*	16 July, 1992
*/

 


struct ik_reg {			/* define board's register set	*/
	u_char latch_func;	/* latched function register	*/
	u_char card_status;	/* interface status register	*/
	u_char diag_data;	/* diag data - copy of last data byte	*/
	u_char dev_status;	/* device status register	*/
	u_char switches;	/* switch config - read only	*/
	u_char pad0 ;
	u_char modes ;		/* special modes - 10111 only	*/
	u_char pad1 ;
};

#define pulse_func card_status	/* write alias - pulsed functions and card stat	*/
#define data_out diag_data	/* write alias - data out and diag data reg	*/

/* latch_func bits read-write */

#define TEST_ENABLE	0x80	/* enable plotterless test mode	*/
#define TEST_READY	0x40	/* sets ready in test mode	*/
#define DEV_RESET	0x20	/* set latched device reset	*/
#define DMA_START	0x10	/* enable board's dma logic	*/
#define DATA_STREAM	 0x8	/* enable TEK mode data streaming	*/
#define INT_ENABLE	 0x4	/* enable interrupts		*/
#define	VERS_MODE_MASK	0x3	/* mask for print/plot and spp mode bits	*/
#define VERS_SPP	 0x2	/* set versatec simultaneous print/plot mode	*/
#define VERS_PLOT	 0x1	/* set versatec plot mode	*/
#define VERS_NORM_PRINT	0x0	/* normal print mode		*/

/* pulse_func bits - write only */

#define SW_ACK		0x80	/* software ack	*/
#define MASTER_CLEAR	0x40	/* board master clear	*/
#define CLR_INT_FLAG	0x20	/* reset interrupt flag	*/
#define PULSE_DEV_RESET	0x10	/* pulse device reset	*/
#define VERS_CLR	 0x8	/* pulse versatec buffer clear	*/
#define VERS_FF		 0x4	/* pulse versatec form feed	*/
#define VERS_EOT	 0x2	/* pulse versatec EOT	*/
#define VERS_LTR	 0x1	/* pulse versatec line terminate	*/

/* card_status bits - read only */

#define MASTER_READY	0x80	/* board and device ready	*/
#define DEV_READY	0x40	/* device ready	*/
#define INTERRUPT_FLAG	0x20	/* interrupt flag	*/
#define DMA_BYTE	0x10	/* byte dma selected in switches	*/
#define DMA_NO_SWAP	0x8	/* byte swapping OFF in switches	*/
#define TEST_PATTERN	 0x4	/* 0=test pattern 0, 1= test pattern 1	*/
#define PLOT_SW_OFF	 0x2	/* 0 if force plot switch is on	*/
#define DEV_TEST_OFF	 0x1	/* 0 if test switch is on (plotterless test running)	*/

/* device_status bits - read only */

#define BOARD_MASK	0xe0	/* masks board type bits	*/
#define VERS_TTL	0x60
#define VERS_DIFF	0xa0
#define CENT		0xc0
#define	DP_TTL		0x40
#define	DP_DIFF		0x80
#define VERS_READY	0x10
#define CENT_BUSY	 0x8
#define PAPER_OUT	 0x4
#define ON_LINE		 0x2
#define CENT_FAULT	 0x1

/* switches bits - read only */ 
#define TERMINATOR	0x80	/* gives a guess at the termination resistor value	*/
#define DMA_CH_MASK	0x70
#define INT_LEVEL_MASK	 0xf

/* mode register bits - read some, write some */

#define ODD_COUNT	0x40	/* 10111 only-set if odd count (discard last byte)	*/
#define	STROBE_INH	0x20	/* 10111 only-disable data strobe (special application)	*/
#define	LEVEL_INTS	0x10	/* 10111 only-enable level interrupts (active low)	*/

/*	if TRI_ENB_SW is off - dma and int drivers & ready logic always enabled		*/

#define	TRI_ENABLE_SW	0x8	/* read only-tri state mode enable switch ON		*/
#define	DMA_TRI_ENB	0x4	/* enables dma RQ driver to bus (if TRI_ENB_SW is on)	*/
#define	INT_TRI_ENB	0x2	/* enables int RQ driver to bus (if TRI_ENB_SW is on)	*/
#define	READY_ENB	0x1	/* enables interface ready logic(if TRI_ENB_SW is on)	*/



/* other internal definitions	*/

#define IK_PRI	PZERO+2		/* priority for sleeps	*/