/*
	ihcp_reg.h

	hp-ux driver for pci hardcopy board - model 10117
	register definition module -- and other defines

	Ikon Corporation
	2617 Western Avenue
	Seattle, WA USA 98121

	phone:	206.728.6465
	fax:	206.728.1633
	www:	http://www.launchsite.com/ikon
*/

/*
	THIS CODE IS OFFERED TO IKON'S CUSTOMERS AT NO CHARGE, WITH THE INTENT
	THAT IT BE USED WITH IKON'S BOARD LEVEL PRODUCTS.  WHILE IKON INTENDS
	TO KEEP THE DRIVER CURRENT WITH HP'S HARDWARE AND OPERATING SYSTEMS,
	AND TO KEEP THE CODE AS BUG FREE AS POSSIBLE, THIS IS NOT GUARANTEED.

	10 November, 1997	initial conversion from solaris

				strategy uses a combination of p-i/o for leading &
				trailing bytes, and dma for long word blocks

				dma chaining is supported

	20 Novemver, 1997	changed DMA_ENABLE to PLX_DMA_ENABLE to avoid collision with
				hpux define in cpu.h

	8 June, 1999		port to 11x:

				make 64 bit safe

				make debugging tunable, rather than a compile time option
				(increases module size, but shouldn't affect performance)
*/

/*
	There are three address ranges supported (and required) by the hardcopy boards:
	configuration space, PLX register space, and IHCP register space.
	We will access the registers using defined offsets from the appropriate address range
	base addresses.  Macros will be used to shorten the typing task somewhat.
*/

/*
	the configuration space offsets and bit definitions are
	provided by hp in pci.h
*/

/*
	plx run-time register offsets - when accessed directly via the
	plx address range
*/

#define	PLX_ENDIAN_REG		0x0C	/* endian control - actually a local config reg - 9080 ONLY	*/
#define	PLX_MBX_0		0x40	/* mailbox registers	*/
#define	PLX_MBX_1		0x44
#define	PLX_MBX_2		0x48
#define	PLX_MBX_3		0x4C
#define	PLX_MBX_4		0x50
#define	PLX_MBX_5		0x54
#define	PLX_MBX_6		0x58
#define	PLX_MBX_7		0x5C
#define	PLX_PTOL_BELL		0x60	/* doorbell regsiters	*/
#define	PLX_LTOP_BELL		0x64
#define	PLX_INT_CSTAT		0x68	/* interrupt control/status regsiter	*/
#define	PLX_EEPROM_USER		0x6C	/* eeprom control and user bits		*/
#define	PLX_DMA_MODE_0		0x80	/* dma channel 0 mode register		*/
#define	PLX_DMA_PCI_ADD_0	0x84	/* pci address for dma transfer		*/
#define	PLX_DMA_LOC_ADD_0	0x88	/* local address for dma transfer	*/
#define	PLX_DMA_COUNT_0		0x8C	/* dma transfer count in bytes		*/
#define	PLX_DMA_DESC_PTR_0	0x90	/* dma descriptor pointer		*/
#define	PLX_DMA_MODE_1		0x94	/* dma channel 1 mode register		*/
#define	PLX_DMA_PCI_ADD_1	0x98	/* pci address for dma transfer		*/
#define	PLX_DMA_LOC_ADD_1	0x9C	/* local address for dma transfer	*/
#define	PLX_DMA_COUNT_1		0xA0	/* dma transfer count in bytes		*/
#define	PLX_DMA_DESC_PTR_1	0xA4	/* dma descriptor pointer		*/
#define	PLX_DMA_CMD_STAT_BOTH	0xA8	/* dma command/status for both channels	combined	*/
#define	PLX_DMA_CMD_STAT_0	0xA8	/* dma command/status for channel 0	*/
#define	PLX_DMA_CMD_STAT_1	0xA9	/* dma command/status for channel 1	*/
#define	PLX_DMA_ARB_REG		0xAC	/* local/dma arbitration register	*/
#define	PLX_DMA_THRESH		0xB0	/* DMA threshold register		*/


/*
	plx run-time register offsets when accesses via window
	in ihcp address space
*/

#define	IPLX_ENDIAN_REG		0x8C	/* endian control - actually a local config reg - 9080 ONLY	*/
#define	IPLX_MBX_0		0xC0	/* mailbox registers	*/
#define	IPLX_MBX_1		0xC4
#define	IPLX_MBX_2		0xC8
#define	IPLX_MBX_3		0xCC
#define	IPLX_MBX_4		0xD0
#define	IPLX_MBX_5		0xD4
#define	IPLX_MBX_6		0xD8
#define	IPLX_MBX_7		0xDC
#define	IPLX_PTOL_BELL		0xE0	/* doorbell regsiters	*/
#define	IPLX_LTOP_BELL		0xE4
#define	IPLX_INT_CSTAT		0xE8	/* interrupt control/status regsiter	*/
#define	IPLX_EEPROM_USER	0xEC	/* eeprom control and user bits		*/
#define	IPLX_DMA_MODE_0		0x100	/* dma channel 0 mode register		*/
#define	IPLX_DMA_PCI_ADD_0	0x104	/* pci address for dma transfer		*/
#define	IPLX_DMA_LOC_ADD_0	0x108	/* local address for dma transfer	*/
#define	IPLX_DMA_COUNT_0	0x10C	/* dma transfer count in bytes		*/
#define	IPLX_DMA_DESC_PTR_0	0x110	/* dma descriptor pointer		*/
#define	IPLX_DMA_MODE_1		0x114	/* dma channel 1 mode register		*/
#define	IPLX_DMA_PCI_ADD_1	0x118	/* pci address for dma transfer		*/
#define	IPLX_DMA_LOC_ADD_1	0x11C	/* local address for dma transfer	*/
#define	IPLX_DMA_COUNT_1	0x120	/* dma transfer count in bytes		*/
#define	IPLX_DMA_DESC_PTR_1	0x124	/* dma descriptor pointer		*/
#define	IPLX_DMA_CMD_STAT	0x128	/* dma command/status for both channels	*/
#define	IPLX_DMA_ARB_REG	0x12C	/* local/dma arbitration register	*/
#define	IPLX_DMA_THRESH		0x130	/* DMA threshold register		*/


/*
	bit definitions for the PLX run-time registers
*/


/*
	endian control register - 9080 ONLY
*/

#define	CONFIG_BIG_ENDIAN	0x00000001	/* causes local accesses to config space to be big endian - NOT USED	*/
#define	MASTER_BIG_ENDIAN	0x00000002	/* direct master big endian - NOT USED	*/
#define	SLAVE_BIG_ENDIAN	0x00000004	/* direct slave access to ihcp space big endian	*/
#define	SLAVE_ROM_BIG_ENDIAN	0x00000008	/* direct slave accesses to rom space big endian - NOT USED	*/
#define	BYTE_LANE_ENDIAN_MODE	0x00000010	/* causes upper word or byte to be used for access to 16 or 8 bit local bus	*/
#define	SLAVE_1_BIG_ENDIAN	0x00000020	/* direct slave accesses to add space 1 big endian - NOT USED	*/
#define	DMA_1_BIG_ENDIAN	0x00000040	/* dma channel 1 accesses big endian	*/
#define	DMA_0_BIG_ENDIAN	0x00000080	/* dma channel 0 accesses big endian	*/

/*
	interrupt control/status register
*/

#define	LSERR_ABORT_INT_ENABLE	0x00000001	/* enables local interrupt on target or master abort	*/
#define	LSERR_PARITY_INT_ENABLE	0x00000002	* enable local interrupt on PCI parity error		*/
#define	PCI_SERR		0x00000004	/* forces assertion of PCI SERR# signal			*/
#define	MAILBOX_INT_ENABLE	0x00000008	/* enables local interrupt on mailbox write from PCI 9080 ONLY		*/
#define	DMA_0_INTERRUPT_SELECT	0x00000010	/* 1 causes dma 0 interrupt to assert PCI interrupt	*/
						/* 0 causes dma 0 interrupt to assert local interrupt	*/
						/* 9080 ONLY for other chips loop local out to local in on board	*/
#define	DMA_1_INTERRUPT_SELECT	0x00000020	/* same as above - for dma channel 1			*/
#define	PCI_INTERRUPT_ENABLE	0x00000100	/* enables pci interrupts				*/
#define	PCI_DB_INT_ENABLE	0x00000200	/* enables pci doorbell interrupts w/pci int enable	*/
#define	PCI_ABORT_INT_ENABLE	0x00000400	/* enables pci interrupt on master or target abort w/pci int enb	*/
#define	PCI_LOCAL_INT_ENABLE	0x00000800	/* enbles local interrupt to cause pci interrupt w/pci int enb		*/
#define	RETRY_ABORT_ENABLE	0x00001000	/* 256 consecutive master retries will cause target abort		*/
#define	PCI_DB_INTERRUPT	0x00002000	/* 1 indicates pci doorbell interrupt is active		*/
#define	PCI_ABORT_INTERRUPT	0x00004000	/* 1 indicates pci abort interrupt is active		*/
#define	LOCAL_INTERRUPT		0x00008000	/* 1 indicates local interrupt is active		*/
#define	LOCAL_INT_OUT_ENABLE	0x00010000	/* enables local interrupt output			*/
#define	LOCAL_DOORBELL_INT_ENB	0x00020000	/* enables local doorbell interrupts w/local int enb	*/
#define	LOCAL_DMA_0_INT_ENABLE	0x00040000	/* enables dma chan 0 local interrupt w/local int enb	*/
#define	LOCAL_DMA_1_INT_ENABLE	0x00080000	/* enables dma chan 1 local interrupt w/local int enb	*/
#define	LOCAL_DB_INTERRRUPT	0x00100000	/* 1 indicates local doorbell interrupt is active	*/
#define	DMA_0_INTERRUPT		0x00200000	/* 1 indicates dma channel 0 interrupt is active	*/
#define	DMA_1_INTERRUPT		0x00400000	/* 1 indicates dma channel 1 interrupt is active	*/
#define	BIST_INTERRUPT		0x00800000	/* 1 indicates that bilt in self test int is active	*/
#define	DIRECT_MASTER_ABORT	0x01000000	/* 1 indicates abort during direct master xfer		*/
#define	DMA_0_ABORT		0x02000000	/* 1 indicates abort during dma chan 0 xfer		*/
#define	DMA_1_ABORT		0x04000000	/* 1 indicates abort during dma chan 1 xfer		*/
#define	RETRY_ABORT		0x08000000	/* 1 indicates abort after 256 retries 			*/
#define	MBX_0_FLAG		0x10000000	/* 1 indicates PCI wrote to mailbox 0 9080 ONLY	*/
#define	MBX_1_FLAG		0x20000000	/* 1 indicates PCI wrote to mailbox 1 9080 ONLY	*/
#define	MBX_2_FLAG		0x40000000	/* 1 indicates PCI wrote to mailbox 2 9080 ONLY	*/
#define	MBX_3_FLAG		0x80000000	/* 1 indicates PCI wrote to mailbox 3 9080 ONLY	*/


/*
	eeprom control, pci command codes, user bits, init control
*/

#define	DMA_READ_CMD_MASK	0x0000000F	/* masks bits used as pci command during dma read	*/
#define	DMA_READ_CMD_DEF	0x0000000E	/* power up default for dma reads		*/

#define	DMA_WRITE_CMD_MASK	0x000000F0	/* masks bits used as pci command during dma write	*/
#define	DMA_WRITE_CMD_DEF	0x00000070	/* power up default for dma writes		*/

#define	MASTER_READ_CMD_MASK	0x00000F00	/* masks bits used as pci command during direct master read	*/
#define	MASTER_READ_CMD_DEF	0x00000600	/* power up default for direct master reads	*/

#define	MASTER_WRITE_CMD_MASK	0x0000F000	/* masks bits used as pci command during direct master write	*/
#define	MASTER_WRITE_CMD_DEF	0x00007000	/* power up default for direct master writes	*/

#define	USER_OUTPUT		0x00010000	/* user output bit	*/
#define	USER_INPUT		0x00020000	/* user input bit	*/
#define	EEPROM_CLOCK		0x01000000	/* toggling this bit generates an eeprom clock	*/
#define	EEPROM_CHIP_SELECT	0x02000000	/* drives the eeprom chip select 		*/
#define	EEPROM_WRITE_BIT	0x04000000	/* write bit to eeprom				*/
#define	EEPROM_READ_BIT		0x08000000	/* read bit from eeprom				*/
#define	EEPROM_PRESENT		0x10000000	/* 1 indicates that an eeprom is present	*/
#define	CONFIGURATION_RELOAD	0x20000000	/* 0-to-1 causes reload of configuration registers from eeprom	*/
#define	PLX_SOFT_RESET		0x40000000	/* holds plx chip reset and aserts local reset out (big hammer!)*/
#define	LOCAL_INIT_DONE		0x80000000	/* local init done - since no local master - this is held at 1 by #NB pin	*/


/*
	dma channels 0 and 1 mode register bits
*/

#define	DMA_BUS_WIDTH_MASK	0x00000003	/* mask for dma local bus width bits	*/
#define	DMA_BUS_8_BIT		0x00000000	/* 8 bit dma bus			*/
#define	DMA_BUS_16_bIT		0x00000001	/* 16 bit dma bus			*/
#define	DMA_BUS_32_BIT		0x00000002	/* 32 bit dma bus			*/

#define	DMA_WAIT_STATE_MASK	0x0000003C	/* mask for local bus wait state count	*/
#define	DMA_WAIT_1		0x00000004	/* one wait state used for current boards	*/

#define	DMA_READY_IN_ENABLE	0x00000040	/* enable ready input during dma	*/
#define	DMA_BTERM_IN_ENABLE	0x00000080	/* enable bterm input during dma	*/
#define	DMA_BURST_ENABLE	0x00000100	/* enable local bursting during dma	*/
#define	DMA_CHAIN_ENABLE	0x00000200	/* enable dma chaining			*/
#define	DMA_DONE_INTERRUPT_ENB	0x00000400	/* enable dma done interrupt		*/
#define	DMA_LOCAL_ADD_HOLD	0x00000800	/* 0 causes local add to increment during dma	*/
#define	DMA_DEMAND_MODE		0x00001000	/* enables demand mode dma (DREQ# input)	*/
#define	DMA_WRITE_INVALID	0x00002000	/* perform write and invalidate cycles 9080 ONLY	*/
#define	DMA_EOT_ENABLE		0x00004000	/* enable eot input 9060SD and 9080 only	*/
#define	DMA_STOP_MODE		0x00008000	/* 0=blast terminates xfer, 1=eot on,	*/
						/* or dreq off in demand mode terminates 9060SD and 9080 ONLY	*/
#define	DMA_CLEAR_COUNT_MODE	0x00010000	/* causes byte count in each descriptor to be zeroed when done 9080 ONLY	*/


/*
	dma pci address registers, local address registers, and
	transfer size registers have no special control bits

	transfer count register is limited to lower 23 bits
	=8Mbyte max xfer per chain list element
*/

#define	DMA_XFER_COUNT_MASK	0x007fffff


/*
	dma channels 0 and 1 descriptor pointer register bits
*/

#define	DMA_CHAIN_IN_PCI_MEM	0x00000001	/* if set, dma chain list in pci memory, otherwise local memory	*/
						/* some boards do not have local memory				*/
#define	DMA_END_OF_CHAIN	0x00000002	/* if set, this chain element is last in list			*/
#define	DMA_LINK_INTERRUPT	0x00000004	/* if set, interrupt when this element's count is exhausted	*/
#define	DMA_INPUT		0x00000008	/* if set, direction of xfer is local to PCI			*/

#define	DMA_NEXT_ADDRESS_MASK	0xfffffff0	/* bit mask for address of next quad word list element		*/


/*
	dma channels 0 and 1 have identical BYTE wide command/status registers
	which may be accessed at separate byte addresses, or as a single 16 or 32
	bit register

	dma channel 0 is at the lower offset, channel 1 is the next higher byte offset

	DMA_ENABLE HAS BEEN RE-NAMED PLX_DMA_ENABLE TO AVOID COLLISION WITH HPUX MACRO IN cpu.h
*/


#define	PLX_DMA_ENABLE		0x01		/* enables the dma channel when 1 - disables (pauses) when 0	*/
#define	DMA_START		0x02		/* 1 starts the dma transfer if enable true			*/
#define	DMA_ABORT		0x04		/* 1 aborts the transfer, leaves enable true			*/
#define	DMA_CLEAR_INTERRUPT	0x08		/* 1 clears the dma interrupt					*/
#define	DMA_DONE		0x10		/* 1 indicates that the dma transfer is complete		*/


/*
	dma arbitration and threshold registers left at
	default of 0 for current board implementations
*/


/*
	ichp (ikon logic portion of board) register offsets
	registers are byte wide in low byte of 32 bit longword
	except 32 bit data out register which is 32 bits wide

	all ihcp registers may be accessed as 32 bit values
*/

#define	IHCP_INTERRUPT_MASK	0x00		/* interrupt mask for ikon portion of logic	*/
#define	IHCP_MODE		0x04		/* mode control for ikon logic			*/
#define	IHCP_DEVICE_CONTROL	0x08		/* device control register			*/
#define	IHCP_INTERFACE_CONTROL	0x0C		/* interface control register			*/
#define	IHCP_INTERFACE_STATUS	0x10		/* interface status register			*/
#define	IHCP_DEVICE_STATUS	0x14		/* device status regsiter			*/
#define	IHCP_REVERSE_DATA	0x18		/* diagnostic and 1284 reverse data register	*/
#define	IHCP_RESERVED		0x1C		/* unused - reserved				*/
#define	IHCP_AUTO_LTR_LOW	0x20		/* low byte of auto-ltr byte count register	*/
#define	IHCP_AUTO_LTR_HIGH	0x30		/* high byte of auto-ltr byte count register	*/
#define	IHCP_8_BIT_DATA_OUT	0x40		/* single data byte write to fifo 		*/
#define	IHCP_COMMAND_OUT	0x48		/* single command byte write to fifo		*/
#define	IHCP_32_BIT_DATA_OUT	0x50		/* quad data byte write to fifo			*/
#define	IHCP_PLX_RUNTIME_BASE	0x80		/* base of plx window in ihcp address range	*/
#define	IHCP_MEMORY_BASE	0x140		/* base of local memory				*/
#define	IHCP_FIFO_BASE		0x1000		/* base of fifo data burst range		*/

/*
	bit definitions for the ikon (ihcp) regsiters
*/	


/*
	interrupt mask register bits
*/

#define	FAULT_INT_ENB		0x01		/* enable centronics fault to cause interrupt	*/
#define	OFFLINE_INT_ENB		0x02		/* enable not selected or offline to interrupt	*/
#define	NOPAPER_INT_ENB		0x04		/* enable paper out to interrupt		*/
#define	FIFO_NOT_FULL_INT_ENB	0x10		/* fifo not full interrupt			*/
#define	FIFO_NOT_HALF_INT_ENB	0x20		/* interrupt if fifo not half full		*/
#define	FIFO_EMPTY_INT_ENB	0x40		/* interrupt if fifo empty			*/
#define	DEV_AND_INT_RDY_INT_ENB	0x80		/* interrupt if device and interface ready	*/


/*
	ihcp mode register bit definitions
*/

#define	SPEED_MASK		0x03		/* mask for handshake speed bits		*/
#define	SPEED_0			0x00		/* fastest speed				*/
#define	SPEED_1			0x01
#define	SPEED_2			0x02
#define	SPEED_3			0x03

#define	BYTE_SWIZZLE		0x04		/* used with plx user output bit to select high	*/
						/* byte of fifo to be output first		*/
#define	V_BURST			0x08		/* synch burst mode for some Versatec machines  */
						/* requires pld218B or later			*/
#define	IGNORE_BUSY		0x10		/* ignore centronics busy input			*/
#define	BUSY_NOT_ACK		0x20		/* use busy for handshake instead of ack	*/
#define	REVERSE_DATA_ENB	0x40		/* set data outputs to high Z			*/
#define	FOUR_EDGE_HANDSHAKE	0x80		/* use ieee 1284 style 4 edge handshake		*/


/*
	device control register bit definitions

	bits are latches - must be set to 0 after use
*/

#define	ASSERT_INIT		0x01		/* assert nINIT to centronics device		*/
#define	UNASSERT_SEL_IN		0x02		/* turns off sel in to centronics device	*/
#define	ASSERT_AUTO_FD		0x04		/* asserts nAUTO FD to centronics device	*/
#define	ASSERT_STROBE		0x08		/* asserts strobe to centronics device		*/
#define	DISABLE_STROBE		0x20		/* disables strobe to device (data will still	*/
						/* be pulled from fifo, but no strobe issued)	*/
#define	DISABLE_READY		0x40		/* forces device ready status false		*/
#define	FORCE_READY		0x80		/* forces device ready status true		*/


/*
	interface control register bit definitions

	bits are latches - must be set to 0 after use
*/

#define	RESET_DEVICE		0x01		/* 1 holds device reset input true		*/
#define	CLEAR_INTERRUPT_FLAG	0x20		/* 1 clears ichp interrupt flag			*/
#define	SOFTWARE_ACK		0x40		/* simulates ack pulse or ready sequence from device	*/
#define	MASTER_CLEAR		0x80		/* master clear of ihcp logic			*/


/*
	interface status register bit definitions
*/

#define	DATA_PATH_8_BIT		0x01		/* set if board is straped for 8 bit data path	*/
#define	PRINT_MODE_OUTPUT	0x02		/* follows state of print mode output AT OUTPUT	*/
#define	FIFO_NOT_FULL		0x04		/* 1 if fifo not full				*/
#define	FIFO_NOT_HALF_FULL	0x08		/* 1 if fifo not half full			*/
#define	FIFO_EMPTY		0x10		/* 1 if fifo empty				*/
#define	INTERRUPT_FLAG		0x20		/* 1 if ihcp logic interrupting			*/
#define	DEVICE_READY		0x40		/* 1 if device ready				*/
#define	DEVICE_AND_INT_READY	0x80		/* 1 if device and interface ready		*/


/*
	device status register bit definitions
*/

#define	FAULT			0x01		/* 1 if fault input is asserted				*/
#define	ONLINE			0x02		/* 1 if device online					*/
#define	PAPER_OUT		0x04		/* 1 if paper out					*/
#define	CENTRONICS_BUSY		0x08		/* 1 if busy input asserted				*/
#define	VERSATEC_READY		0x10		/* 1 if versatec ready input asserted			*/

#define	INTERFACE_STRAP_MASK	0xE0		/* bits that indicate type of interface selected	*/
						/* used internal to the driver - driver also uses	*/
						/* equivalent defines in ..io.h for flag bits, since	*/
						/* flag bits are visible to the outside world via ioctl	*/
#define	VERSATEC_TTL		0x60		/* versatec ttl selected				*/
#define	VERSATEC_DIFFERENTIAL	0xA0		/* versatec differential selected			*/
#define	CENTRONICS		0xC0		/* centronics selected					*/


/*
	command out register bit definitions
*/

#define	VERSATEC_CLEAR		0x41		/* pulse versatec clear output		*/
#define	VERSATEC_FORM_FEED	0x42		/* pulse form feed output		*/
#define	VERSATEC_EOT		0x44		/* pulse e-o-t				*/
#define	VERSATEC_LINE_TERM	0x48		/* pulse line terminate			*/

#define	SET_VERSATEC_MODE	0x20		/* sets mode as determined by versatec mode bits	*/
#define	NORM_PRINT_MODE		0x00		/* normal print mode bits		*/
#define	PLOT_MODE		0x01		/* plot mode bits			*/
#define	SPP_MODE		0x02		/* spp mode bits			*/

#define	SET_IO_MODE		0x00		/* sets mode as determined by i/o mode bits	*/
#define	AUTO_LTR_MODE		0x10		/* auto line terminate mode bits	*/
#define	DATA_STREAMING_MODE	0x01		/* data streaming mode bits		*/


/*
	other useful definitions
*/

/*
	define pci device and vendor IDs for our board
*/

#define	IHCP_VENDOR_ID	0x11d5
#define	IHCP_DEVICE_ID	0x0117

/*
	define "ORDER" for alloc_spinlock kernel call
	this seems to relate to interrupt priority --
	the documentation sucks -- we will set it high to
	try to block our interrupt level during critical
	code segments
*/

#define	IHCP_ORDER	15

/*
	define address in configuration space of plx and ihcp
	base registers (pointers at physical addresses of register sets)
*/


#define	PLX_CONFIG_BASE_ADDR	0x10	/* add of ptr to mem mapped plx registers	*/
#define	IHCP_CONFIG_BASE_ADDR	0x18	/* add of ptr to mem mapped ihcp registers*/

#define	PLX_SIZE	0x100	/* size of plx register set	*/
#define	IHCP_SIZE	0x2000	/* siez of ihcp register set	*/
/*
	mask for revision id portion of class code & rev id config longword
*/

#define	REV_ID_MASK			0xFF

/*
	debug macro

	this version always compiles to if(ihcp_debug)printf...
	the old version compiled to nothing if not in debug mode
	this allows tuning for debug mode at module install time

	requires double quoted arg list - since printf can take
	variable # of arguments
*/

#define	DPRINT(args)	if(ihcp_debug)printf args

/*
	macro definitions for register access and access to iopb space

	HP swizzles bytes between the cpu/memory and the pci device
	we need to pre swizzle to make things work out when doing 32 bit
	access, and when building the iopb list, which will be accessed
	by the dma chaining mechanism

	the user data buffer should be OK, since this is a byte oriented
	device, and the HP swizzle puts the bytes where we want them

	the PLXx macros are used to access plx registers directly
	the IPLXx macros are used to access the plx dma registers via ihcp space -
	which is necessary with the early revs of the plx chip - we could use IHCPx macros
	to do this, but IPLX should be more readable, and it will be easier to find them
	to mod later if necessary for some future rev of the chip

	the configuration accesses will be done explicitly, without macros

	these macros are used to try to preserve as much source compatibility
	as possible with the solaris drivers

	we could save a few machine cycles by using 8 bit accesses for the ihcp
	registers, & using |= and &=, but we will do it this way for consistency
	-- the registers aren't accessed enough for this to cause a measurable
	performance hit --

*/

#define	PLX_GETL(offset)	ihcp_getl(plx_p,offset)
#define	PLX_PUTL(offset,value)	ihcp_putl(plx_p,offset,value)
#define	IPLX_GETL(offset)	ihcp_getl(ihcp_p,offset)
#define	IPLX_PUTL(offset,value)	ihcp_putl(ihcp_p,offset,value)
#define	IHCP_GETL(offset)	ihcp_getl(ihcp_p,offset)
#define	IHCP_PUTL(offset,value)	ihcp_putl(ihcp_p,offset,value)
#define	IOPB_GETL(offset)	ihcp_getl(iopb_p,offset)
#define	IOPB_PUTL(offset,value)	ihcp_putl(iopb_p,offset,value)


/*
	define size of i/o parameter block (link of dma chain list)
	and the offsets of elements of the block from the base address
*/

#define	IOPB_SIZE		0x10		/* 16 bytes per block	*/

#define	IOPB_PCI_ADDRESS	0x00		/* starting pci address	of user buffer block	*/
#define	IOPB_LOCAL_ADDRESS	0x04		/* starting local address	*/
#define	IOPB_TRANSFER_SIZE	0x08		/* number of bytes in this block	*/
#define	IOPB_NEXT_IOPB		0x0c		/* physical address of next iopb in list	*/